Ethernet Stack disturbs EDMA (C6713b)

Hi,

I'm using EDMA to handle my McASP transfers. After these transfers I
chained another EDMA to copy the timer0 to a variable. Both EDMAs have
high priority. I use the difference between two timer values to
calculate the sample rate of McASP.

The Ethernet stack runs and uses only ext. memory. It doesn't use any
EDMA or other DSP hardware. The only code that is connected to an IRQ
are 4 simple software counters.

L2 cache is not used.

I can increase the McASP sample rate up to its max. value and all works
fine. This means about 90% DSP time is used to process McASP data. EDMA
is pretty much maxed out too, because I use it (with low priority) to
access data in ext. RAM.

When there is traffic on the Ethernet the measured sample rate jitters
with up to 50% ( 000 clock cycles)! This has drastic influence on my
algo! The situation get better if ether the McASP sample rate is dropped
to half or the Ethernet traffic is terminated.

Now I wonder how code that runs from ext. memory can influence EDMA? The
reloads for L1 cache should leave some space for high priorty EDMAs to
sneak in. The low priority EDMA handles a lot of data, but is divided
into 16 word packets that are chained together. The Ethernet stack uses
memcpy a lot. Can this cause a delay in EDMA?

TIA

Gustl

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sprz191j.pdf, section 2.1 "EMIF: L2 Cache Operations Block Other EDMA Operations to EMIF"

Even without L2 turned on, I suspect this is what you are running in to.

- Andrew E.

----- Original Message ----
From: Bernhard 'Gustl' Bauer
To: C6x
Sent: Wednesday, March 4, 2009 2:44:29 AM
Subject: [c6x] Ethernet Stack disturbs EDMA (C6713b)

Hi,

I'm using EDMA to handle my McASP transfers. After these transfers I
chained another EDMA to copy the timer0 to a variable. Both EDMAs have
high priority. I use the difference between two timer values to
calculate the sample rate of McASP.

The Ethernet stack runs and uses only ext. memory. It doesn't use any
EDMA or other DSP hardware. The only code that is connected to an IRQ
are 4 simple software counters.

L2 cache is not used.

I can increase the McASP sample rate up to its max. value and all works
fine. This means about 90% DSP time is used to process McASP data. EDMA
is pretty much maxed out too, because I use it (with low priority) to
access data in ext. RAM.

When there is traffic on the Ethernet the measured sample rate jitters
with up to 50% ( 000 clock cycles)! This has drastic influence on my
algo! The situation get better if ether the McASP sample rate is dropped
to half or the Ethernet traffic is terminated.

Now I wonder how code that runs from ext. memory can influence EDMA? The
reloads for L1 cache should leave some space for high priorty EDMAs to
sneak in. The low priority EDMA handles a lot of data, but is divided
into 16 word packets that are chained together. The Ethernet stack uses
memcpy a lot. Can this cause a delay in EDMA?

TIA

Gustl

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