Jeff:
Thanks very much for your reply!
The first question: “If the ADCs and DACs are connected to EMIF, then why
do you need additional GPIO signals? To what pins are the GPIO signals
connected?”
The ADC we used is MAXIM1317. Its reference pdf is:
http://datasheets.maxim-ic.com/en/ds/MAX1316-MAX1326.pdf
The DAC we used is AD5344. Its reference pdf is:
http://www.analog.com/static/imported-files/data_sheets/AD5334_5335_5336_5344.pdf
From that we know that the ADC needs control signals such as /CS /Convst /RD
/EOLC, so we configure Mcbsp as GPIO to send these signals. For example, FSX0
and CLKX0 are configured as /RD and /CS of ADC respectively, FSR0 and CLKR1 are
configured as DAC’s /WR and /LDAC respectively. According to ADC timing,
DSP can be programmed to send these control signals one by one. Then ADC can
work. We searched TMS320C6000 DSP EMIF Reference Guide and found that EMIF
couldn’t send these control signals. We only used EMIF’s data line
ED[0:13]. Above this is the initial thinking, is it right? But now when we use
EMIF, I find /CEn should be connected to ADC/DAC’s /CS to select DSP
memory space. I can’t connect CLKX0 pin and /CEn pin both to the same /CS
of ADC. That’s my puzzle.
The second question: “Well, you have to both read and write the ADCs/DACs,
correct? Normally either /AWE or /ARE is connected (usually just one is
needed).”
Yes, ADC and DAC are all both read/ written. Why only connect /AWE or /ARE?
According to my understanding, /AWE is active-low write strobe for asynchronous
memory interface, /ARE is Active-low read strobe for asynchronous memory
interface. I think we should use /ARE after ADC has finished sampling and use
/AWE after DSP has got a result, so we should make use of both. Is it correct?
If only connect /ARE, how to write to DAC?
“How do you plan to control the WR and RD signals on the ADC and DAC
chips? Using the GPIO pins? That could work, but it's going to make your
code very slow.”
Yes, using GPIO to control them. How to avoid making code slowly?
The last question: “Are you saying you left the /AWE and /ARE pins
NC?”
Yes, on designed ADC/DAC board /AWE and /ARE pins are both NC. If connect /AWE
to /WR of DAC, the original FSR0 (GPIO pin) should be disconnected? /CEn pin of
EMIF should be connected also? When DSP is powered, /CE0 /CE1 /CE2 /CE3 pins in
EMIF are all about 3.3V high level. Is it right? In fact, I tried to connect
/AWE to /WR of DAC without disconnecting FSR0 yesterday, the low level of /WR
was 2.81V and the result was wrong.
>Hi everyone! I'm a newcomer on using TI DSP. Now
I'm working on a project
>that uses Tms320c6713 as argrithom computing unit, one ADC for acquiring
>signals, two DAC for outputing DSP's results. The ADC and DACs are on
one
>piece of circuit we designed. Tms320c6713 collets data from ADC and sends
>data to DAC all through EMIF interface. EMIF is mapped into CE2 space and it
>is configued 16-bit asynchronous interface.
>
>We 've configured two Mcbsps as GPIOs to send out ADC and DAC's
control
>signals, the control signals meet our demands. They can be high or low level
>where we need.
>
>Because I am not familiar with DSP, when we designed our circuit board,
>EMIF's CEn. AWE.ARE pins are all not conneted. So my first quesiton is:
can
>our design work? These EMIF's three pins MUST be conneted? I'm not
sure
>about it.
>
>Today when I debug DAC ( 12 bit), I use this method:
>
>Firstly, write 0x100 16-bit data( each value is 0x0FFF) in program. These
>data are in L2 RAM.
>
>Secondly, send these data to DAC through EMIF in CE2 space, the first
>address is 0xA0000000. Because DAC is 12-bit, the LSB 12 bit is only needed.
>If DAC is disconneted to DSP, I can observe 12 high leves about 3V using
>scope.
>
>Thirdly, running program to send out signlas to control DAC. Unfornately,
>when control signals and data are sent out, I watch memory in address
>0xA0000000, the values are all 0x06600660. It's so strange!! The right
>values should be 0x0FFF0FFF. So the second question is : where does the
>wrong value come from? Is it related to EMIF's /AWE and /CEn pin?
>
>I hope anyone can shed some light on this or point me in the right direction
>todebug this problem.
>
>With kind regards,
_____________________________________
Re: =?windows-1252?Q?Can=92t_get_right_data_when_using_6713_interface_wit?= =?windows-1252?Q?h_a_DAC_converter=21?=
Started by ●July 25, 2009
Reply by ●July 26, 20092009-07-26
Xue Lang-
> Thanks very much for your reply!
> The first question: "If the ADCs and DACs are connected to EMIF,
> then why do you need additional GPIO signals? To
> what pins are the GPIO signals connected?"
> The ADC we used is MAXIM1317. Its reference pdf is:
> http://datasheets.maxim-ic.com/en/ds/MAX1316-MAX1326.pdf
> The DAC we used is AD5344. Its reference pdf is:
> http://www.analog.com/static/imported-files/data_sheets/AD5334_5335_5336_5344.pdf
>
> From that we know that the ADC needs control signals such as
> /CS /Convst /RD /EOLC, so we configure Mcbsp as GPIO to send
> these signals.
/CS and /RD , and /EOLC should be connected to the DSP:
/CS to /CEn, whichever CE space you are using (but
see notes about CPLD below)
/ARE to /RD
/EOLC to an external interrupt pin (for example EINT4)
When reading, the DSP will drive /ARE low, when writing, /ARE will stay high, which is what you want. When a
conversion is complete you can either respond to the interrupt or use it to drive a DMA read.
From just a brief reading of the data sheet, it seems the CONVST signal is a bit more difficult. I assume you are
using "external clock mode", so in that case CONVST should have some relationship to CLK, for example every 15 CLK
cycles, CONVST has a low pulse, according to the data sheet timing diagram. But also, CONVST seems to have some
one-time reset/initialization timing... so my suggestion is use a CPLD and do this:
-run Nx (N from 10 to 20) CLK signal to CPLD
-run one GPIO from DSP to CPLD (probably a
ADC_Reset signal)
-in Verilog CPLD code, divide by N to generate
CLK to ADC
-generate CONVST based on CLK/N and ADC_Reset
A programmable logic device such as the CPLD would allow you to adjust CONVST to meet required Maxim ADC timing... and
you would have N times resolution to make precise adjustments to CONVST as needed.
> For example, FSX0 and CLKX0 are configured as
> /RD and /CS of ADC respectively, FSR0 and CLKR1 are
> configured as DAC’s /WR and /LDAC respectively. According
> to ADC timing, DSP can be programmed to send these control
> signals one by one. Then ADC can work. We searched TMS320C6000
> DSP EMIF Reference Guide and found that EMIF couldn't
> send these control signals.
EMIF is intended to read/write "memory like" peripherals. If the peripheral has a pin that requires one-time
sequence, or precise relationship to an external clock -- as it seems the case for CONVST -- you can't use EMIF for
that.
> We only used EMIF's data line ED[0:13]. Above this is the initial thinking, is it
> right?
Yes.
> But now when we use EMIF, I find /CEn should be connected to ADC/DAC's
> /CS to select DSP memory space.
Yes, but you need at least one high address line to differentiate ADC and DAC, because you have to read/write both
chips. For example, you can use EA[21]. This is another good use of the CPLD; you can run /CEn and EA21 into the
CPLD, and create /ADC_CS and /DAC_CS outputs.
> I can't connect CLKX0 pin and /CEn pin both to the same /CS of ADC. That's my puzzle.
> The second question: "Well, you have to both read and write the ADCs/DACs, correct?
> Normally either /AWE or /ARE is connected (usually just one is needed)."
> Yes, ADC and DAC are all both read/ written. Why only connect /AWE or /ARE? According
> to my understanding, /AWE is active-low write strobe for asynchronous memory
> interface, /ARE is Active-low read strobe for asynchronous memory interface. I think
> we should use /ARE after ADC has finished sampling and use /AWE after DSP has got a
> result, so we should make use of both. Is it correct? If only connect /ARE, how to
> write to DAC?
As noted above, you don't need both /ARE and /AWE connected to a peripheral; in fact, there are very few peripherals
with both /RD and /WR pins, usually they just have one, and that pin is treated as low = read (or write) and high opposite.
> "How do you plan to control the WR and RD signals on the ADC and DAC chips? Using
> the GPIO pins? That could work, but it's going to make your code very slow."
> Yes, using GPIO to control them. How to avoid making code slowly?
Using a GPIO pin is acceptable for one-time, or infrequently used, control functions, such as Reset, shutdown, etc.
But if you use a GPIO pin for every sample access, your code will be so slow as to make your system unusable.
-Jeff
> The last question: "Are you saying you left the /AWE and /ARE pins NC?"
> Yes, on designed ADC/DAC board /AWE and /ARE pins are both NC. If connect /AWE to
> /WR of DAC, the original FSR0 (GPIO pin) should be disconnected? /CEn pin of EMIF
> should be connected also? When DSP is powered, /CE0 /CE1 /CE2 /CE3 pins
> in EMIF are all about 3.3V high level. Is it right? In fact, I tried to connect
> /AWE to /WR of DAC without disconnecting FSR0 yesterday, the low level of /WR was
> 2.81V and the result was wrong.
>
>>Hi everyone! I'm a newcomer on using TI DSP. Now I'm working on a project
>>that uses Tms320c6713 as argrithom computing unit, one ADC for acquiring
>>signals, two DAC for outputing DSP's results. The ADC and DACs are on one
>>piece of circuit we designed. Tms320c6713 collets data from ADC and sends
>>data to DAC all through EMIF interface. EMIF is mapped into CE2 space and it
>>is configued 16-bit asynchronous interface.
>>
>>We 've configured two Mcbsps as GPIOs to send out ADC and DAC's control
>>signals, the control signals meet our demands. They can be high or low level
>>where we need.
>>
>>Because I am not familiar with DSP, when we designed our circuit board,
>>EMIF's CEn. AWE.ARE pins are all not conneted. So my first quesiton is: can
>>our design work? These EMIF's three pins MUST be conneted? I'm not sure
>>about it.
>>
>>Today when I debug DAC ( 12 bit), I use this method:
>>
>>Firstly, write 0x100 16-bit data( each value is 0x0FFF) in program. These
>>data are in L2 RAM.
>>
>>Secondly, send these data to DAC through EMIF in CE2 space, the first
>>address is 0xA0000000. Because DAC is 12-bit, the LSB 12 bit is only needed.
>>If DAC is disconneted to DSP, I can observe 12 high leves about 3V using
>>scope.
>>
>>Thirdly, running program to send out signlas to control DAC. Unfornately,
>>when control signals and data are sent out, I watch memory in address
>>0xA0000000, the values are all 0x06600660. It's so strange!! The right
>>values should be 0x0FFF0FFF. So the second question is : where does the
>>wrong value come from? Is it related to EMIF's /AWE and /CEn pin?
>>
>>I hope anyone can shed some light on this or point me in the right direction
>>todebug this problem.
>>
>>With kind regards,
_____________________________________
> Thanks very much for your reply!
> The first question: "If the ADCs and DACs are connected to EMIF,
> then why do you need additional GPIO signals? To
> what pins are the GPIO signals connected?"
> The ADC we used is MAXIM1317. Its reference pdf is:
> http://datasheets.maxim-ic.com/en/ds/MAX1316-MAX1326.pdf
> The DAC we used is AD5344. Its reference pdf is:
> http://www.analog.com/static/imported-files/data_sheets/AD5334_5335_5336_5344.pdf
>
> From that we know that the ADC needs control signals such as
> /CS /Convst /RD /EOLC, so we configure Mcbsp as GPIO to send
> these signals.
/CS and /RD , and /EOLC should be connected to the DSP:
/CS to /CEn, whichever CE space you are using (but
see notes about CPLD below)
/ARE to /RD
/EOLC to an external interrupt pin (for example EINT4)
When reading, the DSP will drive /ARE low, when writing, /ARE will stay high, which is what you want. When a
conversion is complete you can either respond to the interrupt or use it to drive a DMA read.
From just a brief reading of the data sheet, it seems the CONVST signal is a bit more difficult. I assume you are
using "external clock mode", so in that case CONVST should have some relationship to CLK, for example every 15 CLK
cycles, CONVST has a low pulse, according to the data sheet timing diagram. But also, CONVST seems to have some
one-time reset/initialization timing... so my suggestion is use a CPLD and do this:
-run Nx (N from 10 to 20) CLK signal to CPLD
-run one GPIO from DSP to CPLD (probably a
ADC_Reset signal)
-in Verilog CPLD code, divide by N to generate
CLK to ADC
-generate CONVST based on CLK/N and ADC_Reset
A programmable logic device such as the CPLD would allow you to adjust CONVST to meet required Maxim ADC timing... and
you would have N times resolution to make precise adjustments to CONVST as needed.
> For example, FSX0 and CLKX0 are configured as
> /RD and /CS of ADC respectively, FSR0 and CLKR1 are
> configured as DAC’s /WR and /LDAC respectively. According
> to ADC timing, DSP can be programmed to send these control
> signals one by one. Then ADC can work. We searched TMS320C6000
> DSP EMIF Reference Guide and found that EMIF couldn't
> send these control signals.
EMIF is intended to read/write "memory like" peripherals. If the peripheral has a pin that requires one-time
sequence, or precise relationship to an external clock -- as it seems the case for CONVST -- you can't use EMIF for
that.
> We only used EMIF's data line ED[0:13]. Above this is the initial thinking, is it
> right?
Yes.
> But now when we use EMIF, I find /CEn should be connected to ADC/DAC's
> /CS to select DSP memory space.
Yes, but you need at least one high address line to differentiate ADC and DAC, because you have to read/write both
chips. For example, you can use EA[21]. This is another good use of the CPLD; you can run /CEn and EA21 into the
CPLD, and create /ADC_CS and /DAC_CS outputs.
> I can't connect CLKX0 pin and /CEn pin both to the same /CS of ADC. That's my puzzle.
> The second question: "Well, you have to both read and write the ADCs/DACs, correct?
> Normally either /AWE or /ARE is connected (usually just one is needed)."
> Yes, ADC and DAC are all both read/ written. Why only connect /AWE or /ARE? According
> to my understanding, /AWE is active-low write strobe for asynchronous memory
> interface, /ARE is Active-low read strobe for asynchronous memory interface. I think
> we should use /ARE after ADC has finished sampling and use /AWE after DSP has got a
> result, so we should make use of both. Is it correct? If only connect /ARE, how to
> write to DAC?
As noted above, you don't need both /ARE and /AWE connected to a peripheral; in fact, there are very few peripherals
with both /RD and /WR pins, usually they just have one, and that pin is treated as low = read (or write) and high opposite.
> "How do you plan to control the WR and RD signals on the ADC and DAC chips? Using
> the GPIO pins? That could work, but it's going to make your code very slow."
> Yes, using GPIO to control them. How to avoid making code slowly?
Using a GPIO pin is acceptable for one-time, or infrequently used, control functions, such as Reset, shutdown, etc.
But if you use a GPIO pin for every sample access, your code will be so slow as to make your system unusable.
-Jeff
> The last question: "Are you saying you left the /AWE and /ARE pins NC?"
> Yes, on designed ADC/DAC board /AWE and /ARE pins are both NC. If connect /AWE to
> /WR of DAC, the original FSR0 (GPIO pin) should be disconnected? /CEn pin of EMIF
> should be connected also? When DSP is powered, /CE0 /CE1 /CE2 /CE3 pins
> in EMIF are all about 3.3V high level. Is it right? In fact, I tried to connect
> /AWE to /WR of DAC without disconnecting FSR0 yesterday, the low level of /WR was
> 2.81V and the result was wrong.
>
>>Hi everyone! I'm a newcomer on using TI DSP. Now I'm working on a project
>>that uses Tms320c6713 as argrithom computing unit, one ADC for acquiring
>>signals, two DAC for outputing DSP's results. The ADC and DACs are on one
>>piece of circuit we designed. Tms320c6713 collets data from ADC and sends
>>data to DAC all through EMIF interface. EMIF is mapped into CE2 space and it
>>is configued 16-bit asynchronous interface.
>>
>>We 've configured two Mcbsps as GPIOs to send out ADC and DAC's control
>>signals, the control signals meet our demands. They can be high or low level
>>where we need.
>>
>>Because I am not familiar with DSP, when we designed our circuit board,
>>EMIF's CEn. AWE.ARE pins are all not conneted. So my first quesiton is: can
>>our design work? These EMIF's three pins MUST be conneted? I'm not sure
>>about it.
>>
>>Today when I debug DAC ( 12 bit), I use this method:
>>
>>Firstly, write 0x100 16-bit data( each value is 0x0FFF) in program. These
>>data are in L2 RAM.
>>
>>Secondly, send these data to DAC through EMIF in CE2 space, the first
>>address is 0xA0000000. Because DAC is 12-bit, the LSB 12 bit is only needed.
>>If DAC is disconneted to DSP, I can observe 12 high leves about 3V using
>>scope.
>>
>>Thirdly, running program to send out signlas to control DAC. Unfornately,
>>when control signals and data are sent out, I watch memory in address
>>0xA0000000, the values are all 0x06600660. It's so strange!! The right
>>values should be 0x0FFF0FFF. So the second question is : where does the
>>wrong value come from? Is it related to EMIF's /AWE and /CEn pin?
>>
>>I hope anyone can shed some light on this or point me in the right direction
>>todebug this problem.
>>
>>With kind regards,
_____________________________________
