Hello, could you please help in the following issue? We're configuring EDMA
in the TMS320C6455 in order to send/receive data to/from FPGA via EMIFA bus.
We've found a problem in the EDMA configuration when we are trying to read
from FPGA. We detect in the time diagram that every 20 cycles, the ADS signal
goes high, so the signals CE and OE goes high too. We don't know if there
are some type of limit in the DSP performance when we read from FPGA and we use
EDMA. Could we optimize the read from FPGA in order to maintain ADS low during
the read period from FPGA? In that cases, the read from FPGA would be faster.
We're using sync comm with FPGA.
We send you our EDMA configuration and the time diagram in the read period from
FPGA.
Any suggestion would be very appreciated!
Many Thanks,
Best Regards,
Francisco
Our EDMA configuration is shown below:
EDMA_PARAM5_OPTION = 0x00102305;
/*Option configuration
100000010 0 011 0000 0 1 0 1
PRIV: 0
Reserved: 00
Privid: 0000
ITCCHEN: 0
TCCHEN: 0
ITCINTEN: 0
TCINTEN: 1
RESERVED: 00
TCC: 000010
TCCMODE: 0
FWID: 011
RESERVED: 0000
STATIC: 0
SYNCDIM: 1
DAM: 0
SAM: 1
*/
EDMA_PARAM5_SRC = EMIFA_FPGA_READ_WRITE;
EDMA_PARAM5_BCNT_ACNT = 0x000101FF; //ACNT = 1FF BCNT = 1
EDMA_PARAM5_DST = (DIR_BEGIN_RX + 8);
EDMA_PARAM5_DSTBIDX = 0x00080000; //DSTBIDX = 8 SRCBIDX = 2
EDMA_PARAM5_BCNTRLD = 0x0000FFFF;
EDMA_PARAM5_DSTCIDX = 0x00000000;
EDMA_PARAM5_RSVD = 0x00000001;
EDMA_DCHMAP_35 = 0x000000A0; //paentry = 5
/*
EDMA_DCHMAP_35: 000000000000000000 000000101 00000
Reserved: 000000000000000000
paentry: 000000101
reserved: 00000
*/
EDMA_ESRH = 0x00000008; //Event 5 activated
}
_____________________________________
