Manimaran,
I'm not familiar with the 'rapid IO' process...
For 28 channels, I would have the fpga do all the sampling and have the fpga
present the data to the DSP.
I'm not sure if the selected DSP has an external interface, if it does,
then the DSP can read the finished data as a regular memory access.
however, If the selected DSP does not have an external interface, then I would
use the two McBSP channels
plus a few GPIO bits to 1) indicate when a buffer of a channel of data is
available (fpga->DSP) 2) select which channel of data buffer to input through
the McBSP.(DSP->fpga)
===========================
How much processing does the DSP need to do for each GSM receiver channel?
I would have the fpga implement frame buffers for the GSM data, 2 frame buffers
for each GSM channel so ping pong can be implemented.
Then the DSP has little to do other than controlling the data flow through the
FPGA.
The fpga can perform most of the data capture and pass through in parallel, so
the DSP can concentrate on the control of the fpga.
28 channels of data will mean the DSP can not perform much processing on each
GSM receiver channel and still be able to keep up with the data.
if the fpga handles all the data flow and the DSP only handles the control
operations, then the DSP should be able to easily keep up with the data
flow.
A while back, I did a ISDN receiver that could handle 128 channels of data
within the FPGA.
the DSP had little to do other than control signals to/from the fpga and for
each incomming signal, route that signal out the correct bus out of the fpga.
R. Williams
---------- Original Message -----------
From: "Manimaran Subramanian - ERS, HCL Tech"
To: Richard Williams , sagar
Cc: "c..."
Sent: Tue, 9 Feb 2010 07:29:50 +0530
Subject: RE: [c6x] C64x+: GSM Receiver Implementation on C64x+
>
>
> Thanks Williams
>
> Do you recommand to use McBSP interface between FPGA and DSP for getting IQ
samples from 28 channels?
>
> We want to use RapidIO interface for this purpose? Can you please comment?
>
> Regarding number of IQ samples per symbol
>
> I have calculated
> effective data rate: ( 270.833 Kbits/Sec ) * ( 2 samples/bit) * (16 bit /
sample ) * (2 I and Q data) = 17333 Kbits / sec = 2.111 Mbytes/sec
>
> - Each bit in the burst is sampled 2x times
> - each sample is 16 bit data
> - 2 samples (one I and Q data)
>
> Whether my calculation right or am i missing something
>
>
>
> Regards
> S Manimaran
>
-----------------------------------
From: Richard Williams [r...@lewiscounty.com]
> Sent: Tuesday, February 09, 2010 4:50 AM
> To: Manimaran Subramanian - ERS, HCL Tech; sagar
> Cc: c...
> Subject: RE: [c6x] C64x+: GSM Receiver Implementation on C64x+
> Manimaran,
>
> If I understand your project correctly,
> If you have the McBSP doing the sampling of the incoming data
> If you have the McBSP sampling as several times the bit rate, not just 2x the
bit rate.
> Then the data read from the McBSP will be 16 bits of data.
> I think you could also set the McBSP to handle 32 bits of data at a time,
This would reduce the interrupt rate by 2.
>
> so...
>
> 270.833kbit/sec divide by 16 is approx 17552 interrupts per second.
> and is only approx 17.552k 16bit words per second.
>
> multiply the amount of data by two due to 2 inputs.
>
> You could greatly reduce the number of interrupts by having each McBSP using
DMA to deposit the data into a buffer, say 32k buffers Then you would only have
to service an interrupt when the buffer is full.
>
> By double buffering the two input streams, you would have a significant amount
of time, say 1 second per input stream to process the data.
>
> By making the input buffers larger, say 256k each, you would have several
seconds to process each input buffer, though there would be a lot more data to
process.
>
> R. Williams
>
> ---------- Original Message -----------
> From: "Manimaran Subramanian - ERS, HCL Tech"
> To: sagar
> Cc: "c..."
> Sent: Mon, 8 Feb 2010 13:06:56 +0530
> Subject: RE: [c6x] C64x+: GSM Receiver Implementation on C64x+
>
> >
> >
> > Thanks for your information.
> >
> > I am little confused with your data rate calculation
> >
> > Suppose I need to process 2 GSM channels simultaneously
> >
> > GSM Date rate: 270.833 Kilo bits/ seconds
> >
> > Hence effective data rate: ( 270.833 Kbits/Sec ) * ( 2 samples/bit) * (16
bit / sample ) * (2 IQ data)* (2 channels) = 34666.624 Kbits / sec = 16.927
Mbytes/sec
> >
> > Am I missing anything my calculation?
> >
> > Thanks in advance.
> >
> > Regards
> > S Manimaran
> >
> > From: sagar [mailto:s...@yahoo.co.in]
> > Sent: Monday, February 08, 2010 12:40 PM
> > To: Manimaran Subramanian - ERS, HCL Tech
> > Cc: c...
> > Subject: RE: [c6x] C64x+: GSM Receiver Implementation on C64x+
> >
> > Hi Subramanian,
> > It all depends on how many channels you are processing and what is your
sampling rate and with how many bits you are representing your each I & Q
sample. I didnt worked on 6474 so i dont have any idea of what are the
peripherals and the data rate they supporton the 6474.
> > Suppose i am handling 2 channels so gsm data rate 270.833 if i am getting
upsampled by 2 and each sample represents by 16 samples so it comes like
270.833*2*16=8.667 Mhz so if ur I&Q is interleaved it comes arround 17.333Mhz.
So look into how many channelsur handling and with what sampling rate and number
of bits.
> >
> > best regards
> >
> > --- On Mon, 8/2/10, Manimaran Subramanian - ERS, HCL Tech
wrote:
> >
> > From: Manimaran Subramanian - ERS, HCL Tech
> > Subject: RE: [c6x] C64x+: GSM Receiver Implementation on C64x+
> > To: "sagar"
> > Cc: "c..."
> > Date: Monday, 8 February, 2010, 11:50 AM
> > Thanks sagar for your suggestion
> >
> > We are in the process of evolving interface definition between FPGA and
DSP(C6474)
> >
> > I am seeing two possibility
> >
> > 1. Rapid IO
> >
> > 2. OBSAI
> >
> > Can you please comment?
> >
> > Regards
> > S Manimaran
> >
> > From: sagar [mailto:s...@yahoo.co.in]
> > Sent: Monday, February 08, 2010 11:27 AM
> > To: Manimaran Subramanian - ERS, HCL Tech
> > Cc: c...
> > Subject: Re: [c6x] C64x+: GSM Receiver Implementation on C64x+
> >
> > Hi Subramanian,
> > Typical number of IQ samples required is 2. Of course it depends on your
algorithm and complexity.
> > I didnt get the 2 question.
> > How you interfaced your DSP with FPGA??Your GSM burst will be coming
continuously..so how you take into dsp by ping pong buffering?? It all depends
on how you interfaced your DSP with FPGA. Actually taking into FPGA and Framing
will be done accordingto your interface and send to DSP.
> >
> > --- On Thu, 4/2/10, Manimaran Subramanian - ERS, HCL Tech
wrote:
> >
> > From: Manimaran Subramanian - ERS, HCL Tech
> > Subject: [c6x] C64x+: GSM Receiver Implementation on C64x+
> > To: "c..."
> > Date: Thursday, 4 February, 2010, 4:31 PM
> >
> > Dear All
> >
> > I am in the process of capturing requirements for GSM receiver using C64X+
and DSP needs to be interfaced with FPGA to get an IQ samples.
> >
> > Question:
> >
> > 1. What is the typical number of IQ samples required (i.e., number of
samples per symbol in the burst) i.e., decimation factor
> > 2. What is the suitable interface to receive 30+ duplex channels (Rapid IO
or OBSAI)
> > 3. What is the typical implementation for holding IQ samples. I.e, whether
FPGA holds number of IQ samples and transfer or DSP receives as an when IQ
samples are arrived. I believe the second implementation requires processor
attention each time.
> >
> > Please clarify my doubts or tell me the pointer where I can get the details.
> >
> > Thanks in advance.
> >
> > Regards
> > S Manimaran
> >
> >
> ------- End of Original Message -------
>
DISCLAIMER:
-----------
The contents of this e-mail and any attachment(s) are confidential and intended
for the named recipient(s) only.
It shall not attach any liability on the originator or HCL or its affiliates.
Any views or opinions presented in
this email are solely those of the author and may not necessarily reflect the
opinions of HCL or its affiliates.
Any form of reproduction, dissemination, copying, disclosure, modification,
distribution and / or publication of
this message without the prior written consent of the author of this e-mail is
strictly prohibited. If you have
received this email in error please delete it and notify the sender immediately.
Before opening any mail and
attachments please check them for viruses and
defect.
-----------
>
------- End of Original Message -------
RE: C64x+: GSM Receiver Implementation on C64x+
Started by ●February 9, 2010
Reply by ●February 9, 20102010-02-09
Thanks Williams for quick response.
My DSP (C6474) is 3 core and each running 1GHZ speed has to perform the following operation for all 28 channels simultaneously
1. GMSK demodulation
2. Data de-interleave operation
3. Channel decoding
Hence, as you have mentioned, DSP should concentrate only on the processing part rather than data traffic handling..
DSP has three major interfaces
1. McBSP
2. Rapid IO
3. OBSAI (Antenna IF)
I am also thinking to have ping-pong buffers at FPGA side and read entire IQ samples at a time. In that CPU will get interrupted after bunch of data transfer...I need to work out amount of data to be transferred per burst duration..
Hope I you would have got more clarity on my project.. please share your thoughts..
Thanks in advance.
Regards
S Manimaran
From: Richard Williams [mailto:r...@lewiscounty.com]
Sent: Tuesday, February 09, 2010 10:04 AM
To: Manimaran Subramanian - ERS, HCL Tech; Richard Williams; sagar
Cc: c...
Subject: RE: [c6x] C64x+: GSM Receiver Implementation on C64x+
Manimaran,
I'm not familiar with the 'rapid IO' process...
For 28 channels, I would have the fpga do all the sampling and have the fpga present the data to the DSP.
I'm not sure if the selected DSP has an external interface, if it does, then the DSP can read the finished data as a regular memory access.
however, If the selected DSP does not have an external interface, then I would use the two McBSP channels
plus a few GPIO bits to 1) indicate when a buffer of a channel of data is available (fpga->DSP) 2) select which channel of data buffer to input through the McBSP.(DSP->fpga)
===========================
How much processing does the DSP need to do for each GSM receiver channel?
I would have the fpga implement frame buffers for the GSM data, 2 frame buffers for each GSM channel so ping pong can be implemented.
Then the DSP has little to do other than controlling the data flow through the FPGA.
The fpga can perform most of the data capture and pass through in parallel, so the DSP can concentrate on the control of the fpga.
28 channels of data will mean the DSP can not perform much processing on each GSM receiver channel and still be able to keep up with the data.
if the fpga handles all the data flow and the DSP only handles the control operations, then the DSP should be able to easily keep up with the data flow.
A while back, I did a ISDN receiver that could handle 128 channels of data within the FPGA.
the DSP had little to do other than control signals to/from the fpga and for each incomming signal, route that signal out the correct bus out of the fpga.
R. Williams
---------- Original Message -----------
From: "Manimaran Subramanian - ERS, HCL Tech"
To: Richard Williams , sagar
Cc: "c..."
Sent: Tue, 9 Feb 2010 07:29:50 +0530
Subject: RE: [c6x] C64x+: GSM Receiver Implementation on C64x+
> Thanks Williams
>
> Do you recommand to use McBSP interface between FPGA and DSP for getting IQ samples from 28 channels?
>
> We want to use RapidIO interface for this purpose? Can you please comment?
>
> Regarding number of IQ samples per symbol
>
> I have calculated
> effective data rate: ( 270.833 Kbits/Sec ) * ( 2 samples/bit) * (16 bit / sample ) * (2 I and Q data) = 17333 Kbits / sec = 2.111 Mbytes/sec
>
> - Each bit in the burst is sampled 2x times
> - each sample is 16 bit data
> - 2 samples (one I and Q data)
>
> Whether my calculation right or am i missing something
>
> Regards
> S Manimaran
>
________________________________
From: Richard Williams [r...@lewiscounty.com]
> Sent: Tuesday, February 09, 2010 4:50 AM
> To: Manimaran Subramanian - ERS, HCL Tech; sagar
> Cc: c...
> Subject: RE: [c6x] C64x+: GSM Receiver Implementation on C64x+
> Manimaran,
>
> If I understand your project correctly,
> If you have the McBSP doing the sampling of the incoming data
> If you have the McBSP sampling as several times the bit rate, not just 2x the bit rate.
> Then the data read from the McBSP will be 16 bits of data.
> I think you could also set the McBSP to handle 32 bits of data at a time, This would reduce the interrupt rate by 2.
>
> so...
>
> 270.833kbit/sec divide by 16 is approx 17552 interrupts per second.
> and is only approx 17.552k 16bit words per second.
>
> multiply the amount of data by two due to 2 inputs.
>
> You could greatly reduce the number of interrupts by having each McBSP using DMA to deposit the data into a buffer, say 32k buffers Then you would only have to service an interrupt when the buffer is full.
>
> By double buffering the two input streams, you would have a significant amount of time, say 1 second per input stream to process the data.
>
> By making the input buffers larger, say 256k each, you would have several seconds to process each input buffer, though there would be a lot more data to process.
>
> R. Williams
>
> ---------- Original Message -----------
> From: "Manimaran Subramanian - ERS, HCL Tech"
> To: sagar
> Cc: "c..."
> Sent: Mon, 8 Feb 2010 13:06:56 +0530
> Subject: RE: [c6x] C64x+: GSM Receiver Implementation on C64x+
>
> >
> >
> > Thanks for your information.
> >
> > I am little confused with your data rate calculation
> >
> > Suppose I need to process 2 GSM channels simultaneously
> >
> > GSM Date rate: 270.833 Kilo bits/ seconds
> >
> > Hence effective data rate: ( 270.833 Kbits/Sec ) * ( 2 samples/bit) * (16 bit / sample ) * (2 IQ data)* (2 channels) = 34666.624 Kbits / sec = 16.927 Mbytes/sec
> >
> > Am I missing anything my calculation?
> >
> > Thanks in advance.
> >
> > Regards
> > S Manimaran
> >
> > From: sagar [mailto:s...@yahoo.co.in]
> > Sent: Monday, February 08, 2010 12:40 PM
> > To: Manimaran Subramanian - ERS, HCL Tech
> > Cc: c...
> > Subject: RE: [c6x] C64x+: GSM Receiver Implementation on C64x+
> >
> > Hi Subramanian,
> > It all depends on how many channels you are processing and what is your sampling rate and with how many bits you are representing your each I & Q sample. I didnt worked on 6474 so i dont have any idea of what are the peripherals and the data rate they support on the 6474.
> > Suppose i am handling 2 channels so gsm data rate 270.833 if i am getting upsampled by 2 and each sample represents by 16 samples so it comes like 270.833*2*16=8.667 Mhz so if ur I&Q is interleaved it comes arround 17.333Mhz. So look into how many channels ur handling and with what sampling rate and number of bits.
> >
> > best regards
> >
> > --- On Mon, 8/2/10, Manimaran Subramanian - ERS, HCL Tech > wrote:
> >
> > From: Manimaran Subramanian - ERS, HCL Tech >
> > Subject: RE: [c6x] C64x+: GSM Receiver Implementation on C64x+
> > To: "sagar" >
> > Cc: "c..." >
> > Date: Monday, 8 February, 2010, 11:50 AM
> > Thanks sagar for your suggestion
> >
> > We are in the process of evolving interface definition between FPGA and DSP(C6474)
> >
> > I am seeing two possibility
> >
> > 1. Rapid IO
> >
> > 2. OBSAI
> >
> > Can you please comment?
> >
> > Regards
> > S Manimaran
> >
> > From: sagar [mailto:s...@yahoo.co.in]
> > Sent: Monday, February 08, 2010 11:27 AM
> > To: Manimaran Subramanian - ERS, HCL Tech
> > Cc: c...
> > Subject: Re: [c6x] C64x+: GSM Receiver Implementation on C64x+
> >
> > Hi Subramanian,
> > Typical number of IQ samples required is 2. Of course it depends on your algorithm and complexity.
> > I didnt get the 2 question.
> > How you interfaced your DSP with FPGA??Your GSM burst will be coming continuously..so how you take into dsp by ping pong buffering?? It all depends on how you interfaced your DSP with FPGA. Actually taking into FPGA and Framing will be done according to your interface and send to DSP.
> >
> > --- On Thu, 4/2/10, Manimaran Subramanian - ERS, HCL Tech > wrote:
> >
> > From: Manimaran Subramanian - ERS, HCL Tech >
> > Subject: [c6x] C64x+: GSM Receiver Implementation on C64x+
> > To: "c..." >
> > Date: Thursday, 4 February, 2010, 4:31 PM
> >
> > Dear All
> >
> > I am in the process of capturing requirements for GSM receiver using C64X+ and DSP needs to be interfaced with FPGA to get an IQ samples.
> >
> > Question:
> >
> > 1. What is the typical number of IQ samples required (i.e., number of samples per symbol in the burst) i.e., decimation factor
> > 2. What is the suitable interface to receive 30+ duplex channels (Rapid IO or OBSAI)
> > 3. What is the typical implementation for holding IQ samples. I.e, whether FPGA holds number of IQ samples and transfer or DSP receives as an when IQ samples are arrived. I believe the second implementation requires processor attention each time.
> >
> > Please clarify my doubts or tell me the pointer where I can get the details.
> >
> > Thanks in advance.
> >
> > Regards
> > S Manimaran
> >
> >
> ------- End of Original Message -------
>
DISCLAIMER:
-----------
The contents of this e-mail and any attachment(s) are confidential and intended
for the named recipient(s) only.
It shall not attach any liability on the originator or HCL or its affiliates.
Any views or opinions presented in
this email are solely those of the author and may not necessarily reflect the
opinions of HCL or its affiliates.
Any form of reproduction, dissemination, copying, disclosure, modification,
distribution and / or publication of
this message without the prior written consent of the author of this e-mail is
strictly prohibited. If you have
received this email in error please delete it and notify the sender immediately.
Before opening any mail and
attachments please check them for viruses and
defect.
-----------
>
------- End of Original Message -------
My DSP (C6474) is 3 core and each running 1GHZ speed has to perform the following operation for all 28 channels simultaneously
1. GMSK demodulation
2. Data de-interleave operation
3. Channel decoding
Hence, as you have mentioned, DSP should concentrate only on the processing part rather than data traffic handling..
DSP has three major interfaces
1. McBSP
2. Rapid IO
3. OBSAI (Antenna IF)
I am also thinking to have ping-pong buffers at FPGA side and read entire IQ samples at a time. In that CPU will get interrupted after bunch of data transfer...I need to work out amount of data to be transferred per burst duration..
Hope I you would have got more clarity on my project.. please share your thoughts..
Thanks in advance.
Regards
S Manimaran
From: Richard Williams [mailto:r...@lewiscounty.com]
Sent: Tuesday, February 09, 2010 10:04 AM
To: Manimaran Subramanian - ERS, HCL Tech; Richard Williams; sagar
Cc: c...
Subject: RE: [c6x] C64x+: GSM Receiver Implementation on C64x+
Manimaran,
I'm not familiar with the 'rapid IO' process...
For 28 channels, I would have the fpga do all the sampling and have the fpga present the data to the DSP.
I'm not sure if the selected DSP has an external interface, if it does, then the DSP can read the finished data as a regular memory access.
however, If the selected DSP does not have an external interface, then I would use the two McBSP channels
plus a few GPIO bits to 1) indicate when a buffer of a channel of data is available (fpga->DSP) 2) select which channel of data buffer to input through the McBSP.(DSP->fpga)
===========================
How much processing does the DSP need to do for each GSM receiver channel?
I would have the fpga implement frame buffers for the GSM data, 2 frame buffers for each GSM channel so ping pong can be implemented.
Then the DSP has little to do other than controlling the data flow through the FPGA.
The fpga can perform most of the data capture and pass through in parallel, so the DSP can concentrate on the control of the fpga.
28 channels of data will mean the DSP can not perform much processing on each GSM receiver channel and still be able to keep up with the data.
if the fpga handles all the data flow and the DSP only handles the control operations, then the DSP should be able to easily keep up with the data flow.
A while back, I did a ISDN receiver that could handle 128 channels of data within the FPGA.
the DSP had little to do other than control signals to/from the fpga and for each incomming signal, route that signal out the correct bus out of the fpga.
R. Williams
---------- Original Message -----------
From: "Manimaran Subramanian - ERS, HCL Tech"
To: Richard Williams , sagar
Cc: "c..."
Sent: Tue, 9 Feb 2010 07:29:50 +0530
Subject: RE: [c6x] C64x+: GSM Receiver Implementation on C64x+
> Thanks Williams
>
> Do you recommand to use McBSP interface between FPGA and DSP for getting IQ samples from 28 channels?
>
> We want to use RapidIO interface for this purpose? Can you please comment?
>
> Regarding number of IQ samples per symbol
>
> I have calculated
> effective data rate: ( 270.833 Kbits/Sec ) * ( 2 samples/bit) * (16 bit / sample ) * (2 I and Q data) = 17333 Kbits / sec = 2.111 Mbytes/sec
>
> - Each bit in the burst is sampled 2x times
> - each sample is 16 bit data
> - 2 samples (one I and Q data)
>
> Whether my calculation right or am i missing something
>
> Regards
> S Manimaran
>
________________________________
From: Richard Williams [r...@lewiscounty.com]
> Sent: Tuesday, February 09, 2010 4:50 AM
> To: Manimaran Subramanian - ERS, HCL Tech; sagar
> Cc: c...
> Subject: RE: [c6x] C64x+: GSM Receiver Implementation on C64x+
> Manimaran,
>
> If I understand your project correctly,
> If you have the McBSP doing the sampling of the incoming data
> If you have the McBSP sampling as several times the bit rate, not just 2x the bit rate.
> Then the data read from the McBSP will be 16 bits of data.
> I think you could also set the McBSP to handle 32 bits of data at a time, This would reduce the interrupt rate by 2.
>
> so...
>
> 270.833kbit/sec divide by 16 is approx 17552 interrupts per second.
> and is only approx 17.552k 16bit words per second.
>
> multiply the amount of data by two due to 2 inputs.
>
> You could greatly reduce the number of interrupts by having each McBSP using DMA to deposit the data into a buffer, say 32k buffers Then you would only have to service an interrupt when the buffer is full.
>
> By double buffering the two input streams, you would have a significant amount of time, say 1 second per input stream to process the data.
>
> By making the input buffers larger, say 256k each, you would have several seconds to process each input buffer, though there would be a lot more data to process.
>
> R. Williams
>
> ---------- Original Message -----------
> From: "Manimaran Subramanian - ERS, HCL Tech"
> To: sagar
> Cc: "c..."
> Sent: Mon, 8 Feb 2010 13:06:56 +0530
> Subject: RE: [c6x] C64x+: GSM Receiver Implementation on C64x+
>
> >
> >
> > Thanks for your information.
> >
> > I am little confused with your data rate calculation
> >
> > Suppose I need to process 2 GSM channels simultaneously
> >
> > GSM Date rate: 270.833 Kilo bits/ seconds
> >
> > Hence effective data rate: ( 270.833 Kbits/Sec ) * ( 2 samples/bit) * (16 bit / sample ) * (2 IQ data)* (2 channels) = 34666.624 Kbits / sec = 16.927 Mbytes/sec
> >
> > Am I missing anything my calculation?
> >
> > Thanks in advance.
> >
> > Regards
> > S Manimaran
> >
> > From: sagar [mailto:s...@yahoo.co.in]
> > Sent: Monday, February 08, 2010 12:40 PM
> > To: Manimaran Subramanian - ERS, HCL Tech
> > Cc: c...
> > Subject: RE: [c6x] C64x+: GSM Receiver Implementation on C64x+
> >
> > Hi Subramanian,
> > It all depends on how many channels you are processing and what is your sampling rate and with how many bits you are representing your each I & Q sample. I didnt worked on 6474 so i dont have any idea of what are the peripherals and the data rate they support on the 6474.
> > Suppose i am handling 2 channels so gsm data rate 270.833 if i am getting upsampled by 2 and each sample represents by 16 samples so it comes like 270.833*2*16=8.667 Mhz so if ur I&Q is interleaved it comes arround 17.333Mhz. So look into how many channels ur handling and with what sampling rate and number of bits.
> >
> > best regards
> >
> > --- On Mon, 8/2/10, Manimaran Subramanian - ERS, HCL Tech > wrote:
> >
> > From: Manimaran Subramanian - ERS, HCL Tech >
> > Subject: RE: [c6x] C64x+: GSM Receiver Implementation on C64x+
> > To: "sagar" >
> > Cc: "c..." >
> > Date: Monday, 8 February, 2010, 11:50 AM
> > Thanks sagar for your suggestion
> >
> > We are in the process of evolving interface definition between FPGA and DSP(C6474)
> >
> > I am seeing two possibility
> >
> > 1. Rapid IO
> >
> > 2. OBSAI
> >
> > Can you please comment?
> >
> > Regards
> > S Manimaran
> >
> > From: sagar [mailto:s...@yahoo.co.in]
> > Sent: Monday, February 08, 2010 11:27 AM
> > To: Manimaran Subramanian - ERS, HCL Tech
> > Cc: c...
> > Subject: Re: [c6x] C64x+: GSM Receiver Implementation on C64x+
> >
> > Hi Subramanian,
> > Typical number of IQ samples required is 2. Of course it depends on your algorithm and complexity.
> > I didnt get the 2 question.
> > How you interfaced your DSP with FPGA??Your GSM burst will be coming continuously..so how you take into dsp by ping pong buffering?? It all depends on how you interfaced your DSP with FPGA. Actually taking into FPGA and Framing will be done according to your interface and send to DSP.
> >
> > --- On Thu, 4/2/10, Manimaran Subramanian - ERS, HCL Tech > wrote:
> >
> > From: Manimaran Subramanian - ERS, HCL Tech >
> > Subject: [c6x] C64x+: GSM Receiver Implementation on C64x+
> > To: "c..." >
> > Date: Thursday, 4 February, 2010, 4:31 PM
> >
> > Dear All
> >
> > I am in the process of capturing requirements for GSM receiver using C64X+ and DSP needs to be interfaced with FPGA to get an IQ samples.
> >
> > Question:
> >
> > 1. What is the typical number of IQ samples required (i.e., number of samples per symbol in the burst) i.e., decimation factor
> > 2. What is the suitable interface to receive 30+ duplex channels (Rapid IO or OBSAI)
> > 3. What is the typical implementation for holding IQ samples. I.e, whether FPGA holds number of IQ samples and transfer or DSP receives as an when IQ samples are arrived. I believe the second implementation requires processor attention each time.
> >
> > Please clarify my doubts or tell me the pointer where I can get the details.
> >
> > Thanks in advance.
> >
> > Regards
> > S Manimaran
> >
> >
> ------- End of Original Message -------
>
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