Re: UART on DSK6713

k..No i haven't checked the DXR line for what is being transmitted.I thought to do this, but how to do it?? i don't know.Plz suggest a way to chk DXR and DRR.

As for McBSP clock, i have set CLKGDV according to the formula in spra633, i.e. (CPU freq)/(baud rate*16)-1.As per this one, CPU frequency of 6713 is 225MHZ, Baud rate i keep 19,200, so CLKGDV comes 731 approx.Do i need to set any other CLK??? which one???

Here I am posting the configuration part of McBSP and EDMA which has the information regarding, MSB or LSB and CLKGDV.

/*******************************************************************/
/* void ConfigEDMA(void): set up EDMA channel 14/15 for UART Xmit */
/*******************************************************************/
void ConfigEDMA(void)
{
EDMA_configArgs(hEdma14,

/* OPT Setup */
EDMA_OPT_RMK(
EDMA_OPT_PRI_HIGH, /* 1 */
EDMA_OPT_ESIZE_16BIT, /* 01 */
EDMA_OPT_2DS_NO, /* 0 */
EDMA_OPT_SUM_INC, /* 01 */
EDMA_OPT_2DD_NO, /* 0 */
EDMA_OPT_DUM_NONE, /* 00 */
EDMA_OPT_TCINT_YES, /* 1 */
EDMA_OPT_TCC_OF(14), /* 14 */
EDMA_OPT_LINK_NO, /* 0 */
EDMA_OPT_FS_NO /* 0 */
),

/* SRC Setup */
EDMA_SRC_RMK((Uint32) xmitbuf), /*xmitbuf address*/

/* CNT Setup */
EDMA_CNT_RMK(
EDMA_CNT_FRMCNT_DEFAULT,
EDMA_CNT_ELECNT_OF(BUFFER_SIZE*11)
),

/* DST Setup */
EDMA_DST_RMK(MCBSP_getXmtAddr(hMcbsp1)),

/* IDX Setup */
EDMA_IDX_RMK(0,0),

/* RLD Setup */
EDMA_RLD_RMK(0,0)
);

EDMA_configArgs(hEdma15,

/* OPT Setup */

EDMA_OPT_RMK(
EDMA_OPT_PRI_HIGH, /* 1 */
EDMA_OPT_ESIZE_16BIT, /* 01 */
EDMA_OPT_2DS_NO, /* 0 */
EDMA_OPT_SUM_NONE, /* 00 */
EDMA_OPT_2DD_NO, /* 0 */
EDMA_OPT_DUM_INC, /* 01 */
EDMA_OPT_TCINT_YES, /* 1 */
EDMA_OPT_TCC_OF(15), /* 15 */
EDMA_OPT_LINK_NO, /* 0 */
EDMA_OPT_FS_NO /* 0 */
),

/* SRC Setup */
EDMA_SRC_RMK(MCBSP_getRcvAddr(hMcbsp1)),

/* CNT Setup */
EDMA_CNT_RMK(0, (BUFFER_SIZE * 11)),

/* DST Setup */
EDMA_DST_RMK((Uint32) recvbuf), /*recvbuf address*/

/* IDX Setup */
EDMA_IDX_RMK(0,0),

/* RLD Setup */
EDMA_RLD_RMK(0,0)
);

} /* End of ConfigEDMA() */

*******************************************************************/
/* void ConfigMcBSP(void): Setup for McBSP Configuration */
/*******************************************************************/
void ConfigMcBSP(void)
{

MCBSP_Config mcbspCfg1 = {

/* SPCR Setup */
MCBSP_SPCR_RMK(
MCBSP_SPCR_FREE_YES, /* 1 */
MCBSP_SPCR_SOFT_DEFAULT, /* 0 */
MCBSP_SPCR_FRST_DEFAULT, /* 0 */
MCBSP_SPCR_GRST_DEFAULT, /* 0 */
MCBSP_SPCR_XINTM_XRDY, /* 00 */
MCBSP_SPCR_XSYNCERR_DEFAULT, /* 0 */
MCBSP_SPCR_XRST_DEFAULT, /* 0 */
MCBSP_SPCR_DLB_OFF, /* 0 */
MCBSP_SPCR_RJUST_RZF, /* 00 */
MCBSP_SPCR_CLKSTP_DISABLE, /* 0 */
MCBSP_SPCR_DXENA_OFF, /* 0 */
MCBSP_SPCR_RINTM_RRDY, /* 00 */
MCBSP_SPCR_RSYNCERR_DEFAULT, /* 0 */
MCBSP_SPCR_RRST_DEFAULT /* 0 */
),

/* RCR Setup */
MCBSP_RCR_RMK(
MCBSP_RCR_RPHASE_DUAL, /* 1 */
MCBSP_RCR_RFRLEN2_OF(1), /* 00010 */
MCBSP_RCR_RWDLEN2_8BIT, /* 000 */
MCBSP_RCR_RCOMPAND_MSB, /* 00 */
MCBSP_RCR_RFIG_YES, /* 1 */
MCBSP_RCR_RDATDLY_1BIT, /* 01 */
MCBSP_RCR_RFRLEN1_OF(8), /* 01000 */
MCBSP_RCR_RWDLEN1_16BIT, /* 010 */
MCBSP_RCR_RWDREVRS_DISABLE /* 0 */
),

/* XCR Setup */

MCBSP_XCR_RMK(
MCBSP_XCR_XPHASE_DUAL, /* 1 */
MCBSP_XCR_XFRLEN2_OF(1), /* 00010 */
MCBSP_XCR_XWDLEN2_8BIT, /* 000 */
MCBSP_XCR_XCOMPAND_MSB, /* 00 */
MCBSP_XCR_XFIG_YES, /* 1 */
MCBSP_XCR_XDATDLY_0BIT, /* 00 */
MCBSP_XCR_XFRLEN1_OF(8), /* 01000 */
MCBSP_XCR_XWDLEN1_16BIT, /* 010 */
MCBSP_XCR_XWDREVRS_DISABLE /* 0 */
),
#endif

/* SRGR Setup */
MCBSP_SRGR_RMK(
MCBSP_SRGR_GSYNC_FREE, /* 0 */
MCBSP_SRGR_CLKSP_RISING, /* 0*/
MCBSP_SRGR_CLKSM_INTERNAL, /* 1 */
MCBSP_SRGR_FSGM_DXR2XSR, /* 0 */
MCBSP_SRGR_FPER_DEFAULT, /* 0 */
MCBSP_SRGR_FWID_DEFAULT, /* 0 */
MCBSP_SRGR_CLKGDV_OF(732) /* CLKGDV */

),

/* MCR Setup */
MCBSP_MCR_DEFAULT,
/* RCER Setup */
MCBSP_RCER_DEFAULT,

/* XCER Setup */
MCBSP_XCER_DEFAULT,

/* PCR Setup */
MCBSP_PCR_RMK(
MCBSP_PCR_XIOEN_SP, /* 0 */
MCBSP_PCR_RIOEN_SP, /* 0 */
MCBSP_PCR_FSXM_INTERNAL, /* 1 */
MCBSP_PCR_FSRM_EXTERNAL, /* 0 */
MCBSP_PCR_CLKXM_OUTPUT, /* 1 */
MCBSP_PCR_CLKRM_OUTPUT, /* 1 */
MCBSP_PCR_CLKSSTAT_0, /* 0 */
MCBSP_PCR_DXSTAT_0, /* 0 */
MCBSP_PCR_FSXP_ACTIVELOW, /* 1 */
MCBSP_PCR_FSRP_ACTIVELOW, /* 1 */
MCBSP_PCR_CLKXP_RISING, /* 0 */
MCBSP_PCR_CLKRP_FALLING /* 0 */
)
};

MCBSP_config(hMcbsp1, &mcbspCfg1);

} /* end of Config_McBSP(void) */
And as for "Did you implement the part about replacing every bit to xmit'd with 4 occurrances of that bit?

Did you implement the part about using a 'majority rules' to extract each bit from the recv'd bit stream?" . Though the logic used is this , but j had not chked it, as until and unless the recvbuf data is correcct and equal to xmitbuf data,how will this logic be correct???

_____________________________________ Start a New Thread

Avin,

do you have a logic analyzer, I think you stated that you do?
If so, it is very simple..
connect the trigger lead from the logic analyzer to the FSX pin of the DSP.
connect a data lead from the logic analyzer to the DX pin of the DSP.
Save the result as a file. (to a floppy)
attach that file to your post.

For completeness, you may also want to capture the CLKX signal line with the logic analyzer.

You may also want to experiment with the info at:
2.5.5.7 32-Bit Bit Reversal: RWDREVRS, XWDREVRS in SPRUGJ6C to see if you can fix the data reversal problem.



R. Williams

---------- Original Message -----------
From: a...@gmail.com
To: c...
Sent: Thu, 22 Apr 2010 00:39:41 -0400
Subject: [c6x] Re: UART on DSK6713

>
>
> k..No i haven't checked the DXR line for what is being transmitted.I thought to do this, but how to do it?? i don't know.Plz suggest a way to chk DXR and DRR.
>
> As for McBSP clock, i have set CLKGDV according to the formula in spra633, i.e. (CPU freq)/(baud rate*16)-1.As per this one, CPU frequency of 6713 is 225MHZ, Baud rate i keep 19,200, so CLKGDV comes 731 approx.Do i need to set any other CLK??? which one???
>
> Here I am posting the configuration part of McBSP and EDMA which has the information regarding, MSB or LSB and CLKGDV.
>
> /*******************************************************************/
> /* void ConfigEDMA(void): set up EDMA channel 14/15 for UART Xmit */
> /*******************************************************************/
> void ConfigEDMA(void)
> {
> EDMA_configArgs(hEdma14,
>
> /* OPT Setup */
> EDMA_OPT_RMK(
> EDMA_OPT_PRI_HIGH, /* 1 */
> EDMA_OPT_ESIZE_16BIT, /* 01 */
> EDMA_OPT_2DS_NO, /* 0 */
> EDMA_OPT_SUM_INC, /* 01 */
> EDMA_OPT_2DD_NO, /* 0 */
> EDMA_OPT_DUM_NONE, /* 00 */
> EDMA_OPT_TCINT_YES, /* 1 */
> EDMA_OPT_TCC_OF(14), /* 14 */
> EDMA_OPT_LINK_NO, /* 0 */
> EDMA_OPT_FS_NO /* 0 */
> ),
>
> /* SRC Setup */
> EDMA_SRC_RMK((Uint32) xmitbuf), /*xmitbuf address*/
>
> /* CNT Setup */
> EDMA_CNT_RMK(
> EDMA_CNT_FRMCNT_DEFAULT,
> EDMA_CNT_ELECNT_OF(BUFFER_SIZE*11)
> ),
>
> /* DST Setup */
> EDMA_DST_RMK(MCBSP_getXmtAddr(hMcbsp1)),
>
> /* IDX Setup */
> EDMA_IDX_RMK(0,0),
>
> /* RLD Setup */
> EDMA_RLD_RMK(0,0)
> );
>
> EDMA_configArgs(hEdma15,
>
> /* OPT Setup */
>
> EDMA_OPT_RMK(
> EDMA_OPT_PRI_HIGH, /* 1 */
> EDMA_OPT_ESIZE_16BIT, /* 01 */
> EDMA_OPT_2DS_NO, /* 0 */
> EDMA_OPT_SUM_NONE, /* 00 */
> EDMA_OPT_2DD_NO, /* 0 */
> EDMA_OPT_DUM_INC, /* 01 */
> EDMA_OPT_TCINT_YES, /* 1 */
> EDMA_OPT_TCC_OF(15), /* 15 */
> EDMA_OPT_LINK_NO, /* 0 */
> EDMA_OPT_FS_NO /* 0 */
> ),
>
> /* SRC Setup */
> EDMA_SRC_RMK(MCBSP_getRcvAddr(hMcbsp1)),
>
> /* CNT Setup */
> EDMA_CNT_RMK(0, (BUFFER_SIZE * 11)),
>
> /* DST Setup */
> EDMA_DST_RMK((Uint32) recvbuf), /*recvbuf address*/
>
> /* IDX Setup */
> EDMA_IDX_RMK(0,0),
>
> /* RLD Setup */
> EDMA_RLD_RMK(0,0)
> );
>
> } /* End of ConfigEDMA() */
>
> *******************************************************************/
> /* void ConfigMcBSP(void): Setup for McBSP Configuration */
> /*******************************************************************/
> void ConfigMcBSP(void)
> {
>
> MCBSP_Config mcbspCfg1 = {
>
> /* SPCR Setup */
> MCBSP_SPCR_RMK(
> MCBSP_SPCR_FREE_YES, /* 1 */
> MCBSP_SPCR_SOFT_DEFAULT, /* 0 */
> MCBSP_SPCR_FRST_DEFAULT, /* 0 */
> MCBSP_SPCR_GRST_DEFAULT, /* 0 */
> MCBSP_SPCR_XINTM_XRDY, /* 00 */
> MCBSP_SPCR_XSYNCERR_DEFAULT, /* 0 */
> MCBSP_SPCR_XRST_DEFAULT, /* 0 */
> MCBSP_SPCR_DLB_OFF, /* 0 */
> MCBSP_SPCR_RJUST_RZF, /* 00 */
> MCBSP_SPCR_CLKSTP_DISABLE, /* 0 */
> MCBSP_SPCR_DXENA_OFF, /* 0 */
> MCBSP_SPCR_RINTM_RRDY, /* 00 */
> MCBSP_SPCR_RSYNCERR_DEFAULT, /* 0 */
> MCBSP_SPCR_RRST_DEFAULT /* 0 */
> ),
>
> /* RCR Setup */
> MCBSP_RCR_RMK(
> MCBSP_RCR_RPHASE_DUAL, /* 1 */
> MCBSP_RCR_RFRLEN2_OF(1), /* 00010 */
> MCBSP_RCR_RWDLEN2_8BIT, /* 000 */
> MCBSP_RCR_RCOMPAND_MSB, /* 00 */
> MCBSP_RCR_RFIG_YES, /* 1 */
> MCBSP_RCR_RDATDLY_1BIT, /* 01 */
> MCBSP_RCR_RFRLEN1_OF(8), /* 01000 */
> MCBSP_RCR_RWDLEN1_16BIT, /* 010 */
> MCBSP_RCR_RWDREVRS_DISABLE /* 0 */
> ),
>
> /* XCR Setup */
>
> MCBSP_XCR_RMK(
> MCBSP_XCR_XPHASE_DUAL, /* 1 */
> MCBSP_XCR_XFRLEN2_OF(1), /* 00010 */
> MCBSP_XCR_XWDLEN2_8BIT, /* 000 */
> MCBSP_XCR_XCOMPAND_MSB, /* 00 */
> MCBSP_XCR_XFIG_YES, /* 1 */
> MCBSP_XCR_XDATDLY_0BIT, /* 00 */
> MCBSP_XCR_XFRLEN1_OF(8), /* 01000 */
> MCBSP_XCR_XWDLEN1_16BIT, /* 010 */
> MCBSP_XCR_XWDREVRS_DISABLE /* 0 */
> ),
> #endif
>
> /* SRGR Setup */
> MCBSP_SRGR_RMK(
> MCBSP_SRGR_GSYNC_FREE, /* 0 */
> MCBSP_SRGR_CLKSP_RISING, /* 0*/
> MCBSP_SRGR_CLKSM_INTERNAL, /* 1 */
> MCBSP_SRGR_FSGM_DXR2XSR, /* 0 */
> MCBSP_SRGR_FPER_DEFAULT, /* 0 */
> MCBSP_SRGR_FWID_DEFAULT, /* 0 */
> MCBSP_SRGR_CLKGDV_OF(732) /* CLKGDV */
>
> ),
>
> /* MCR Setup */
> MCBSP_MCR_DEFAULT,
> /* RCER Setup */
> MCBSP_RCER_DEFAULT,
>
> /* XCER Setup */
> MCBSP_XCER_DEFAULT,
>
> /* PCR Setup */
> MCBSP_PCR_RMK(
> MCBSP_PCR_XIOEN_SP, /* 0 */
> MCBSP_PCR_RIOEN_SP, /* 0 */
> MCBSP_PCR_FSXM_INTERNAL, /* 1 */
> MCBSP_PCR_FSRM_EXTERNAL, /* 0 */
> MCBSP_PCR_CLKXM_OUTPUT, /* 1 */
> MCBSP_PCR_CLKRM_OUTPUT, /* 1 */
> MCBSP_PCR_CLKSSTAT_0, /* 0 */
> MCBSP_PCR_DXSTAT_0, /* 0 */
> MCBSP_PCR_FSXP_ACTIVELOW, /* 1 */
> MCBSP_PCR_FSRP_ACTIVELOW, /* 1 */
> MCBSP_PCR_CLKXP_RISING, /* 0 */
> MCBSP_PCR_CLKRP_FALLING /* 0 */
> )
> };
>
> MCBSP_config(hMcbsp1, &mcbspCfg1);
>
> } /* end of Config_McBSP(void) */
>
> And as for "Did you implement the part about replacing every bit to xmit'd with 4 occurrances of that bit?
>
> Did you implement the part about using a 'majority rules' to extract each bit from the recv'd bit stream?" . Though the logic used is this , but j had not chked it, as until and unless the recvbuf data is correcct and equal to xmitbuf data,how will this logic be correct???
------- End of Original Message ------- Start a New Thread

Avin,

Perhaps I was not clear on how to check the actual signal being transmitted.

The HOW is simple.

Use a oscilloscope or logic analyzer.
Connect the signals of interest to the inputs of the logic analyzer (or 'scope).

mod the application program to send the 'M' over and over and over.
run the program.
enable the logic analyzer.
view the actual signal details on the logic analyzer screen.

R. Williams

---------- Original Message -----------
From: a...@gmail.com
To: c...
Sent: Thu, 22 Apr 2010 00:39:41 -0400
Subject: [c6x] Re: UART on DSK6713

>
>
> k..No i haven't checked the DXR line for what is being transmitted.I thought to do this, but how to do it?? i don't know.Plz suggest a way to chk DXR and DRR.
>
> As for McBSP clock, i have set CLKGDV according to the formula in spra633, i.e. (CPU freq)/(baud rate*16)-1.As per this one, CPU frequency of 6713 is 225MHZ, Baud rate i keep 19,200, so CLKGDV comes 731 approx.Do i need to set any other CLK??? which one???
>
> Here I am posting the configuration part of McBSP and EDMA which has the information regarding, MSB or LSB and CLKGDV.
>
> /*******************************************************************/
> /* void ConfigEDMA(void): set up EDMA channel 14/15 for UART Xmit */
> /*******************************************************************/
> void ConfigEDMA(void)
> {
> EDMA_configArgs(hEdma14,
>
> /* OPT Setup */
> EDMA_OPT_RMK(
> EDMA_OPT_PRI_HIGH, /* 1 */
> EDMA_OPT_ESIZE_16BIT, /* 01 */
> EDMA_OPT_2DS_NO, /* 0 */
> EDMA_OPT_SUM_INC, /* 01 */
> EDMA_OPT_2DD_NO, /* 0 */
> EDMA_OPT_DUM_NONE, /* 00 */
> EDMA_OPT_TCINT_YES, /* 1 */
> EDMA_OPT_TCC_OF(14), /* 14 */
> EDMA_OPT_LINK_NO, /* 0 */
> EDMA_OPT_FS_NO /* 0 */
> ),
>
> /* SRC Setup */
> EDMA_SRC_RMK((Uint32) xmitbuf), /*xmitbuf address*/
>
> /* CNT Setup */
> EDMA_CNT_RMK(
> EDMA_CNT_FRMCNT_DEFAULT,
> EDMA_CNT_ELECNT_OF(BUFFER_SIZE*11)
> ),
>
> /* DST Setup */
> EDMA_DST_RMK(MCBSP_getXmtAddr(hMcbsp1)),
>
> /* IDX Setup */
> EDMA_IDX_RMK(0,0),
>
> /* RLD Setup */
> EDMA_RLD_RMK(0,0)
> );
>
> EDMA_configArgs(hEdma15,
>
> /* OPT Setup */
>
> EDMA_OPT_RMK(
> EDMA_OPT_PRI_HIGH, /* 1 */
> EDMA_OPT_ESIZE_16BIT, /* 01 */
> EDMA_OPT_2DS_NO, /* 0 */
> EDMA_OPT_SUM_NONE, /* 00 */
> EDMA_OPT_2DD_NO, /* 0 */
> EDMA_OPT_DUM_INC, /* 01 */
> EDMA_OPT_TCINT_YES, /* 1 */
> EDMA_OPT_TCC_OF(15), /* 15 */
> EDMA_OPT_LINK_NO, /* 0 */
> EDMA_OPT_FS_NO /* 0 */
> ),
>
> /* SRC Setup */
> EDMA_SRC_RMK(MCBSP_getRcvAddr(hMcbsp1)),
>
> /* CNT Setup */
> EDMA_CNT_RMK(0, (BUFFER_SIZE * 11)),
>
> /* DST Setup */
> EDMA_DST_RMK((Uint32) recvbuf), /*recvbuf address*/
>
> /* IDX Setup */
> EDMA_IDX_RMK(0,0),
>
> /* RLD Setup */
> EDMA_RLD_RMK(0,0)
> );
>
> } /* End of ConfigEDMA() */
>
> *******************************************************************/
> /* void ConfigMcBSP(void): Setup for McBSP Configuration */
> /*******************************************************************/
> void ConfigMcBSP(void)
> {
>
> MCBSP_Config mcbspCfg1 = {
>
> /* SPCR Setup */
> MCBSP_SPCR_RMK(
> MCBSP_SPCR_FREE_YES, /* 1 */
> MCBSP_SPCR_SOFT_DEFAULT, /* 0 */
> MCBSP_SPCR_FRST_DEFAULT, /* 0 */
> MCBSP_SPCR_GRST_DEFAULT, /* 0 */
> MCBSP_SPCR_XINTM_XRDY, /* 00 */
> MCBSP_SPCR_XSYNCERR_DEFAULT, /* 0 */
> MCBSP_SPCR_XRST_DEFAULT, /* 0 */
> MCBSP_SPCR_DLB_OFF, /* 0 */
> MCBSP_SPCR_RJUST_RZF, /* 00 */
> MCBSP_SPCR_CLKSTP_DISABLE, /* 0 */
> MCBSP_SPCR_DXENA_OFF, /* 0 */
> MCBSP_SPCR_RINTM_RRDY, /* 00 */
> MCBSP_SPCR_RSYNCERR_DEFAULT, /* 0 */
> MCBSP_SPCR_RRST_DEFAULT /* 0 */
> ),
>
> /* RCR Setup */
> MCBSP_RCR_RMK(
> MCBSP_RCR_RPHASE_DUAL, /* 1 */
> MCBSP_RCR_RFRLEN2_OF(1), /* 00010 */
> MCBSP_RCR_RWDLEN2_8BIT, /* 000 */
> MCBSP_RCR_RCOMPAND_MSB, /* 00 */
> MCBSP_RCR_RFIG_YES, /* 1 */
> MCBSP_RCR_RDATDLY_1BIT, /* 01 */
> MCBSP_RCR_RFRLEN1_OF(8), /* 01000 */
> MCBSP_RCR_RWDLEN1_16BIT, /* 010 */
> MCBSP_RCR_RWDREVRS_DISABLE /* 0 */
> ),
>
> /* XCR Setup */
>
> MCBSP_XCR_RMK(
> MCBSP_XCR_XPHASE_DUAL, /* 1 */
> MCBSP_XCR_XFRLEN2_OF(1), /* 00010 */
> MCBSP_XCR_XWDLEN2_8BIT, /* 000 */
> MCBSP_XCR_XCOMPAND_MSB, /* 00 */
> MCBSP_XCR_XFIG_YES, /* 1 */
> MCBSP_XCR_XDATDLY_0BIT, /* 00 */
> MCBSP_XCR_XFRLEN1_OF(8), /* 01000 */
> MCBSP_XCR_XWDLEN1_16BIT, /* 010 */
> MCBSP_XCR_XWDREVRS_DISABLE /* 0 */
> ),
> #endif
>
> /* SRGR Setup */
> MCBSP_SRGR_RMK(
> MCBSP_SRGR_GSYNC_FREE, /* 0 */
> MCBSP_SRGR_CLKSP_RISING, /* 0*/
> MCBSP_SRGR_CLKSM_INTERNAL, /* 1 */
> MCBSP_SRGR_FSGM_DXR2XSR, /* 0 */
> MCBSP_SRGR_FPER_DEFAULT, /* 0 */
> MCBSP_SRGR_FWID_DEFAULT, /* 0 */
> MCBSP_SRGR_CLKGDV_OF(732) /* CLKGDV */
>
> ),
>
> /* MCR Setup */
> MCBSP_MCR_DEFAULT,
> /* RCER Setup */
> MCBSP_RCER_DEFAULT,
>
> /* XCER Setup */
> MCBSP_XCER_DEFAULT,
>
> /* PCR Setup */
> MCBSP_PCR_RMK(
> MCBSP_PCR_XIOEN_SP, /* 0 */
> MCBSP_PCR_RIOEN_SP, /* 0 */
> MCBSP_PCR_FSXM_INTERNAL, /* 1 */
> MCBSP_PCR_FSRM_EXTERNAL, /* 0 */
> MCBSP_PCR_CLKXM_OUTPUT, /* 1 */
> MCBSP_PCR_CLKRM_OUTPUT, /* 1 */
> MCBSP_PCR_CLKSSTAT_0, /* 0 */
> MCBSP_PCR_DXSTAT_0, /* 0 */
> MCBSP_PCR_FSXP_ACTIVELOW, /* 1 */
> MCBSP_PCR_FSRP_ACTIVELOW, /* 1 */
> MCBSP_PCR_CLKXP_RISING, /* 0 */
> MCBSP_PCR_CLKRP_FALLING /* 0 */
> )
> };
>
> MCBSP_config(hMcbsp1, &mcbspCfg1);
>
> } /* end of Config_McBSP(void) */
>
> And as for "Did you implement the part about replacing every bit to xmit'd with 4 occurrances of that bit?
>
> Did you implement the part about using a 'majority rules' to extract each bit from the recv'd bit stream?" . Though the logic used is this , but j had not chked it, as until and unless the recvbuf data is correcct and equal to xmitbuf data,how will this logic be correct???
------- End of Original Message ------- Start a New Thread

K..Yestrday was holiday so didnt wrk.Going to chk it now.Will post by evening.

On 4/23/10, Richard Williams wrote:
> Avin,
>
> Perhaps I was not clear on how to check the actual signal being transmitted.
>
> The HOW is simple.
>
> Use a oscilloscope or logic analyzer.
> Connect the signals of interest to the inputs of the logic analyzer (or
> 'scope).
>
> mod the application program to send the 'M' over and over and over.
> run the program.
> enable the logic analyzer.
> view the actual signal details on the logic analyzer screen.
>
> R. Williams
>
> ---------- Original Message -----------
> From: a...@gmail.com
> To: c...
> Sent: Thu, 22 Apr 2010 00:39:41 -0400
> Subject: [c6x] Re: UART on DSK6713
>
>> k..No i haven't checked the DXR line for what is being transmitted.I
>> thought to do this, but how to do it?? i don't know.Plz suggest a way to
>> chk DXR and DRR.
>>
>> As for McBSP clock, i have set CLKGDV according to the formula in spra633,
>> i.e. (CPU freq)/(baud rate*16)-1.As per this one, CPU frequency of 6713 is
>> 225MHZ, Baud rate i keep 19,200, so CLKGDV comes 731 approx.Do i need to
>> set any other CLK??? which one???
>>
>> Here I am posting the configuration part of McBSP and EDMA which has the
>> information regarding, MSB or LSB and CLKGDV.
>>
>> /*******************************************************************/
>> /* void ConfigEDMA(void): set up EDMA channel 14/15 for UART Xmit */
>> /*******************************************************************/
>> void ConfigEDMA(void)
>> {
>> EDMA_configArgs(hEdma14,
>>
>> /* OPT Setup */
>> EDMA_OPT_RMK(
>> EDMA_OPT_PRI_HIGH, /* 1 */
>> EDMA_OPT_ESIZE_16BIT, /* 01 */
>> EDMA_OPT_2DS_NO, /* 0 */
>> EDMA_OPT_SUM_INC, /* 01 */
>> EDMA_OPT_2DD_NO, /* 0 */
>> EDMA_OPT_DUM_NONE, /* 00 */
>> EDMA_OPT_TCINT_YES, /* 1 */
>> EDMA_OPT_TCC_OF(14), /* 14 */
>> EDMA_OPT_LINK_NO, /* 0 */
>> EDMA_OPT_FS_NO /* 0 */
>> ),
>>
>> /* SRC Setup */
>> EDMA_SRC_RMK((Uint32) xmitbuf), /*xmitbuf address*/
>>
>> /* CNT Setup */
>> EDMA_CNT_RMK(
>> EDMA_CNT_FRMCNT_DEFAULT,
>> EDMA_CNT_ELECNT_OF(BUFFER_SIZE*11)
>> ),
>>
>> /* DST Setup */
>> EDMA_DST_RMK(MCBSP_getXmtAddr(hMcbsp1)),
>>
>> /* IDX Setup */
>> EDMA_IDX_RMK(0,0),
>>
>> /* RLD Setup */
>> EDMA_RLD_RMK(0,0)
>> );
>>
>> EDMA_configArgs(hEdma15,
>>
>> /* OPT Setup */
>>
>> EDMA_OPT_RMK(
>> EDMA_OPT_PRI_HIGH, /* 1 */
>> EDMA_OPT_ESIZE_16BIT, /* 01 */
>> EDMA_OPT_2DS_NO, /* 0 */
>> EDMA_OPT_SUM_NONE, /* 00 */
>> EDMA_OPT_2DD_NO, /* 0 */
>> EDMA_OPT_DUM_INC, /* 01 */
>> EDMA_OPT_TCINT_YES, /* 1 */
>> EDMA_OPT_TCC_OF(15), /* 15 */
>> EDMA_OPT_LINK_NO, /* 0 */
>> EDMA_OPT_FS_NO /* 0 */
>> ),
>>
>> /* SRC Setup */
>> EDMA_SRC_RMK(MCBSP_getRcvAddr(hMcbsp1)),
>>
>> /* CNT Setup */
>> EDMA_CNT_RMK(0, (BUFFER_SIZE * 11)),
>>
>> /* DST Setup */
>> EDMA_DST_RMK((Uint32) recvbuf), /*recvbuf address*/
>>
>> /* IDX Setup */
>> EDMA_IDX_RMK(0,0),
>>
>> /* RLD Setup */
>> EDMA_RLD_RMK(0,0)
>> );
>>
>> } /* End of ConfigEDMA() */
>>
>> *******************************************************************/
>> /* void ConfigMcBSP(void): Setup for McBSP Configuration */
>> /*******************************************************************/
>> void ConfigMcBSP(void)
>> {
>>
>> MCBSP_Config mcbspCfg1 = {
>>
>> /* SPCR Setup */
>> MCBSP_SPCR_RMK(
>> MCBSP_SPCR_FREE_YES, /* 1 */
>> MCBSP_SPCR_SOFT_DEFAULT, /* 0 */
>> MCBSP_SPCR_FRST_DEFAULT, /* 0 */
>> MCBSP_SPCR_GRST_DEFAULT, /* 0 */
>> MCBSP_SPCR_XINTM_XRDY, /* 00 */
>> MCBSP_SPCR_XSYNCERR_DEFAULT, /* 0 */
>> MCBSP_SPCR_XRST_DEFAULT, /* 0 */
>> MCBSP_SPCR_DLB_OFF, /* 0 */
>> MCBSP_SPCR_RJUST_RZF, /* 00 */
>> MCBSP_SPCR_CLKSTP_DISABLE, /* 0 */
>> MCBSP_SPCR_DXENA_OFF, /* 0 */
>> MCBSP_SPCR_RINTM_RRDY, /* 00 */
>> MCBSP_SPCR_RSYNCERR_DEFAULT, /* 0 */
>> MCBSP_SPCR_RRST_DEFAULT /* 0 */
>> ),
>>
>> /* RCR Setup */
>> MCBSP_RCR_RMK(
>> MCBSP_RCR_RPHASE_DUAL, /* 1 */
>> MCBSP_RCR_RFRLEN2_OF(1), /* 00010 */
>> MCBSP_RCR_RWDLEN2_8BIT, /* 000 */
>> MCBSP_RCR_RCOMPAND_MSB, /* 00 */
>> MCBSP_RCR_RFIG_YES, /* 1 */
>> MCBSP_RCR_RDATDLY_1BIT, /* 01 */
>> MCBSP_RCR_RFRLEN1_OF(8), /* 01000 */
>> MCBSP_RCR_RWDLEN1_16BIT, /* 010 */
>> MCBSP_RCR_RWDREVRS_DISABLE /* 0 */
>> ),
>>
>> /* XCR Setup */
>>
>> MCBSP_XCR_RMK(
>> MCBSP_XCR_XPHASE_DUAL, /* 1 */
>> MCBSP_XCR_XFRLEN2_OF(1), /* 00010 */
>> MCBSP_XCR_XWDLEN2_8BIT, /* 000 */
>> MCBSP_XCR_XCOMPAND_MSB, /* 00 */
>> MCBSP_XCR_XFIG_YES, /* 1 */
>> MCBSP_XCR_XDATDLY_0BIT, /* 00 */
>> MCBSP_XCR_XFRLEN1_OF(8), /* 01000 */
>> MCBSP_XCR_XWDLEN1_16BIT, /* 010 */
>> MCBSP_XCR_XWDREVRS_DISABLE /* 0 */
>> ),
>> #endif
>>
>> /* SRGR Setup */
>> MCBSP_SRGR_RMK(
>> MCBSP_SRGR_GSYNC_FREE, /* 0 */
>> MCBSP_SRGR_CLKSP_RISING, /* 0*/
>> MCBSP_SRGR_CLKSM_INTERNAL, /* 1 */
>> MCBSP_SRGR_FSGM_DXR2XSR, /* 0 */
>> MCBSP_SRGR_FPER_DEFAULT, /* 0 */
>> MCBSP_SRGR_FWID_DEFAULT, /* 0 */
>> MCBSP_SRGR_CLKGDV_OF(732) /* CLKGDV */
>>
>> ),
>>
>> /* MCR Setup */
>> MCBSP_MCR_DEFAULT,
>> /* RCER Setup */
>> MCBSP_RCER_DEFAULT,
>>
>> /* XCER Setup */
>> MCBSP_XCER_DEFAULT,
>>
>> /* PCR Setup */
>> MCBSP_PCR_RMK(
>> MCBSP_PCR_XIOEN_SP, /* 0 */
>> MCBSP_PCR_RIOEN_SP, /* 0 */
>> MCBSP_PCR_FSXM_INTERNAL, /* 1 */
>> MCBSP_PCR_FSRM_EXTERNAL, /* 0 */
>> MCBSP_PCR_CLKXM_OUTPUT, /* 1 */
>> MCBSP_PCR_CLKRM_OUTPUT, /* 1 */
>> MCBSP_PCR_CLKSSTAT_0, /* 0 */
>> MCBSP_PCR_DXSTAT_0, /* 0 */
>> MCBSP_PCR_FSXP_ACTIVELOW, /* 1 */
>> MCBSP_PCR_FSRP_ACTIVELOW, /* 1 */
>> MCBSP_PCR_CLKXP_RISING, /* 0 */
>> MCBSP_PCR_CLKRP_FALLING /* 0 */
>> )
>> };
>>
>> MCBSP_config(hMcbsp1, &mcbspCfg1);
>>
>> } /* end of Config_McBSP(void) */
>>
>> And as for "Did you implement the part about replacing every bit to xmit'd
>> with 4 occurrances of that bit?
>>
>> Did you implement the part about using a 'majority rules' to extract each
>> bit from the recv'd bit stream?" . Though the logic used is this , but j
>> had not chked it, as until and unless the recvbuf data is correcct and
>> equal to xmitbuf data,how will this logic be correct???
> ------- End of Original Message -------
--
AVINASH JHA

_____________________________________ Start a New Thread

the data from logic analyzer.

channel had DXR pin, cahnnel 2 had FSX pin, Channnel 3 had DRR pin.
chk plz.

On 4/22/10, Richard Williams wrote:
>
> Avin,
>
> do you have a logic analyzer, I think you stated that you do?
> If so, it is very simple..
> connect the trigger lead from the logic analyzer to the FSX pin of the DSP.
>
> connect a data lead from the logic analyzer to the DX pin of the DSP.
> Save the result as a file. (to a floppy)
> attach that file to your post.
> For completeness, you may also want to capture the CLKX signal line with
> the logic analyzer.
> You may also want to experiment with the info at:
> 2.5.5.7 32-Bit Bit Reversal: RWDREVRS, XWDREVRS in SPRUGJ6C to see if you
> can fix the data reversal problem.
> R. Williams
>
> *---------- Original Message -----------*
> From: a...@gmail.com
> To: c...
> Sent: Thu, 22 Apr 2010 00:39:41 -0400
> Subject: [c6x] Re: UART on DSK6713
>
> >
> >
> > k..No i haven't checked the DXR line for what is being transmitted.I
> thought to do this, but how to do it?? i don't know.Plz suggest a way to chk
> DXR and DRR.
> >
> > As for McBSP clock, i have set CLKGDV according to the formula in
> spra633, i.e. (CPU freq)/(baud rate*16)-1.As per this one, CPU frequency of
> 6713 is 225MHZ, Baud rate i keep 19,200, so CLKGDV comes 731 approx.Do i
> need to set any other CLK??? which one???
> >
> > Here I am posting the configuration part of McBSP and EDMA which has the
> information regarding, MSB or LSB and CLKGDV.
> >
> > /*******************************************************************/
> > /* void ConfigEDMA(void): set up EDMA channel 14/15 for UART Xmit */
> > /*******************************************************************/
> > void ConfigEDMA(void)
> > {
> > EDMA_configArgs(hEdma14,
> >
> > /* OPT Setup */
> > EDMA_OPT_RMK(
> > EDMA_OPT_PRI_HIGH, /* 1 */
> > EDMA_OPT_ESIZE_16BIT, /* 01 */
> > EDMA_OPT_2DS_NO, /* 0 */
> > EDMA_OPT_SUM_INC, /* 01 */
> > EDMA_OPT_2DD_NO, /* 0 */
> > EDMA_OPT_DUM_NONE, /* 00 */
> > EDMA_OPT_TCINT_YES, /* 1 */
> > EDMA_OPT_TCC_OF(14), /* 14 */
> > EDMA_OPT_LINK_NO, /* 0 */
> > EDMA_OPT_FS_NO /* 0 */
> > ),
> >
> > /* SRC Setup */
> > EDMA_SRC_RMK((Uint32) xmitbuf), /*xmitbuf address*/
> >
> > /* CNT Setup */
> > EDMA_CNT_RMK(
> > EDMA_CNT_FRMCNT_DEFAULT,
> > EDMA_CNT_ELECNT_OF(BUFFER_SIZE*11)
> > ),
> >
> > /* DST Setup */
> > EDMA_DST_RMK(MCBSP_getXmtAddr(hMcbsp1)),
> >
> > /* IDX Setup */
> > EDMA_IDX_RMK(0,0),
> >
> > /* RLD Setup */
> > EDMA_RLD_RMK(0,0)
> > );
> >
> > EDMA_configArgs(hEdma15,
> >
> > /* OPT Setup */
> >
> > EDMA_OPT_RMK(
> > EDMA_OPT_PRI_HIGH, /* 1 */
> > EDMA_OPT_ESIZE_16BIT, /* 01 */
> > EDMA_OPT_2DS_NO, /* 0 */
> > EDMA_OPT_SUM_NONE, /* 00 */
> > EDMA_OPT_2DD_NO, /* 0 */
> > EDMA_OPT_DUM_INC, /* 01 */
> > EDMA_OPT_TCINT_YES, /* 1 */
> > EDMA_OPT_TCC_OF(15), /* 15 */
> > EDMA_OPT_LINK_NO, /* 0 */
> > EDMA_OPT_FS_NO /* 0 */
> > ),
> >
> > /* SRC Setup */
> > EDMA_SRC_RMK(MCBSP_getRcvAddr(hMcbsp1)),
> >
> > /* CNT Setup */
> > EDMA_CNT_RMK(0, (BUFFER_SIZE * 11)),
> >
> > /* DST Setup */
> > EDMA_DST_RMK((Uint32) recvbuf), /*recvbuf address*/
> >
> > /* IDX Setup */
> > EDMA_IDX_RMK(0,0),
> >
> > /* RLD Setup */
> > EDMA_RLD_RMK(0,0)
> > );
> >
> > } /* End of ConfigEDMA() */
> >
> > *******************************************************************/
> > /* void ConfigMcBSP(void): Setup for McBSP Configuration */
> > /*******************************************************************/
> > void ConfigMcBSP(void)
> > {
> >
> > MCBSP_Config mcbspCfg1 = {
> >
> > /* SPCR Setup */
> > MCBSP_SPCR_RMK(
> > MCBSP_SPCR_FREE_YES, /* 1 */
> > MCBSP_SPCR_SOFT_DEFAULT, /* 0 */
> > MCBSP_SPCR_FRST_DEFAULT, /* 0 */
> > MCBSP_SPCR_GRST_DEFAULT, /* 0 */
> > MCBSP_SPCR_XINTM_XRDY, /* 00 */
> > MCBSP_SPCR_XSYNCERR_DEFAULT, /* 0 */
> > MCBSP_SPCR_XRST_DEFAULT, /* 0 */
> > MCBSP_SPCR_DLB_OFF, /* 0 */
> > MCBSP_SPCR_RJUST_RZF, /* 00 */
> > MCBSP_SPCR_CLKSTP_DISABLE, /* 0 */
> > MCBSP_SPCR_DXENA_OFF, /* 0 */
> > MCBSP_SPCR_RINTM_RRDY, /* 00 */
> > MCBSP_SPCR_RSYNCERR_DEFAULT, /* 0 */
> > MCBSP_SPCR_RRST_DEFAULT /* 0 */
> > ),
> >
> > /* RCR Setup */
> > MCBSP_RCR_RMK(
> > MCBSP_RCR_RPHASE_DUAL, /* 1 */
> > MCBSP_RCR_RFRLEN2_OF(1), /* 00010 */
> > MCBSP_RCR_RWDLEN2_8BIT, /* 000 */
> > MCBSP_RCR_RCOMPAND_MSB, /* 00 */
> > MCBSP_RCR_RFIG_YES, /* 1 */
> > MCBSP_RCR_RDATDLY_1BIT, /* 01 */
> > MCBSP_RCR_RFRLEN1_OF(8), /* 01000 */
> > MCBSP_RCR_RWDLEN1_16BIT, /* 010 */
> > MCBSP_RCR_RWDREVRS_DISABLE /* 0 */
> > ),
> >
> > /* XCR Setup */
> >
> > MCBSP_XCR_RMK(
> > MCBSP_XCR_XPHASE_DUAL, /* 1 */
> > MCBSP_XCR_XFRLEN2_OF(1), /* 00010 */
> > MCBSP_XCR_XWDLEN2_8BIT, /* 000 */
> > MCBSP_XCR_XCOMPAND_MSB, /* 00 */
> > MCBSP_XCR_XFIG_YES, /* 1 */
> > MCBSP_XCR_XDATDLY_0BIT, /* 00 */
> > MCBSP_XCR_XFRLEN1_OF(8), /* 01000 */
> > MCBSP_XCR_XWDLEN1_16BIT, /* 010 */
> > MCBSP_XCR_XWDREVRS_DISABLE /* 0 */
> > ),
> > #endif
> >
> > /* SRGR Setup */
> > MCBSP_SRGR_RMK(
> > MCBSP_SRGR_GSYNC_FREE, /* 0 */
> > MCBSP_SRGR_CLKSP_RISING, /* 0*/
> > MCBSP_SRGR_CLKSM_INTERNAL, /* 1 */
> > MCBSP_SRGR_FSGM_DXR2XSR, /* 0 */
> > MCBSP_SRGR_FPER_DEFAULT, /* 0 */
> > MCBSP_SRGR_FWID_DEFAULT, /* 0 */
> > MCBSP_SRGR_CLKGDV_OF(732) /* CLKGDV */
> >
> > ),
> >
> > /* MCR Setup */
> > MCBSP_MCR_DEFAULT,
> > /* RCER Setup */
> > MCBSP_RCER_DEFAULT,
> >
> > /* XCER Setup */
> > MCBSP_XCER_DEFAULT,
> >
> > /* PCR Setup */
> > MCBSP_PCR_RMK(
> > MCBSP_PCR_XIOEN_SP, /* 0 */
> > MCBSP_PCR_RIOEN_SP, /* 0 */
> > MCBSP_PCR_FSXM_INTERNAL, /* 1 */
> > MCBSP_PCR_FSRM_EXTERNAL, /* 0 */
> > MCBSP_PCR_CLKXM_OUTPUT, /* 1 */
> > MCBSP_PCR_CLKRM_OUTPUT, /* 1 */
> > MCBSP_PCR_CLKSSTAT_0, /* 0 */
> > MCBSP_PCR_DXSTAT_0, /* 0 */
> > MCBSP_PCR_FSXP_ACTIVELOW, /* 1 */
> > MCBSP_PCR_FSRP_ACTIVELOW, /* 1 */
> > MCBSP_PCR_CLKXP_RISING, /* 0 */
> > MCBSP_PCR_CLKRP_FALLING /* 0 */
> > )
> > };
> >
> > MCBSP_config(hMcbsp1, &mcbspCfg1);
> >
> > } /* end of Config_McBSP(void) */
> >
> > And as for "Did you implement the part about replacing every bit to
> xmit'd with 4 occurrances of that bit?
> >
> > Did you implement the part about using a 'majority rules' to extract each
> bit from the recv'd bit stream?" . Though the logic used is this , but j had
> not chked it, as until and unless the recvbuf data is correcct and equal to
> xmitbuf data,how will this logic be correct???
> >
> >
> *------- End of Original Message -------*
>

--
AVINASH JHA Start a New Thread

Avin,

I looked through the data you sent.
all 10000 rows.
Then I plotted the data into a chart with several different views.

There is NO valid data of any outputs from the signals produced by the McBSP in any of those rows.

All the time is near 0, which may be acceptable.
All the voltages are near 0 which is not acceptable.

Is this just an error in the selection of the data or is it characteristic.

If this data is characteristic, then the source code is a long ways from being correct as no McBSP output is being produced.

R. Williams

---------- Original Message -----------
From: avinash jha
To: Richard Williams
Cc: c...
Sent: Fri, 23 Apr 2010 17:19:07 +0530
Subject: Re: [c6x] Re: UART on DSK6713 [1 Attachment]

>
>
> [Attachment(s) from avinash jha included below]
>
> the data from logic analyzer.
>
> channel had DXR pin, cahnnel 2 had FSX pin, Channnel 3 had DRR pin.
> chk plz.
>
> On 4/22/10, Richard Williams wrote:
> Avin,
>
> do you have a logic analyzer, I think you stated that you do?
> If so, it is very simple..
> connect the trigger lead from the logic analyzer to the FSX pin of the DSP.
> connect a data lead from the logic analyzer to the DX pin of the DSP.
> Save the result as a file. (to a floppy)
> attach that file to your post.
>
> For completeness, you may also want to capture the CLKX signal line with the logic analyzer.
>
> You may also want to experiment with the info at:
> 2.5.5.7 32-Bit Bit Reversal: RWDREVRS, XWDREVRS in SPRUGJ6C to see if you can fix the data reversal problem.
>
>
>
> R. Williams
>
> ---------- Original Message -----------
> From: a...@gmail.com
> To: c...
> Sent: Thu, 22 Apr 2010 00:39:41 -0400
> Subject: [c6x] Re: UART on DSK6713
>
> >
> > > k..No i haven't checked the DXR line for what is being transmitted.I thought to do this, but how to do it?? i don't know.Plz suggest a way to chk DXR and DRR.
> >
> > As for McBSP clock, i have set CLKGDV according to the formula in spra633, i.e. (CPU freq)/(baud rate*16)-1.As per this one, CPU frequency of 6713 is 225MHZ, Baud rate i keep 19,200, so CLKGDV comes 731 approx.Do i need to set any other CLK??? which one???
> >
> > Here I am posting the configuration part of McBSP and EDMA which has the information regarding, MSB or LSB and CLKGDV.
> >
> > /*******************************************************************/
> > /* void ConfigEDMA(void): set up EDMA channel 14/15 for UART Xmit */
> > /*******************************************************************/
> > void ConfigEDMA(void)
> > {
> > EDMA_configArgs(hEdma14,
> >
> > /* OPT Setup */
> > EDMA_OPT_RMK(
> > EDMA_OPT_PRI_HIGH, /* 1 */
> > EDMA_OPT_ESIZE_16BIT, /* 01 */
> > EDMA_OPT_2DS_NO, /* 0 */
> > EDMA_OPT_SUM_INC, /* 01 */
> > EDMA_OPT_2DD_NO, /* 0 */
> > EDMA_OPT_DUM_NONE, /* 00 */
> > EDMA_OPT_TCINT_YES, /* 1 */
> > EDMA_OPT_TCC_OF(14), /* 14 */
> > EDMA_OPT_LINK_NO, /* 0 */
> > EDMA_OPT_FS_NO /* 0 */
> > ),
> >
> > /* SRC Setup */
> > EDMA_SRC_RMK((Uint32) xmitbuf), /*xmitbuf address*/
> >
> > /* CNT Setup */
> > EDMA_CNT_RMK(
> > EDMA_CNT_FRMCNT_DEFAULT,
> > EDMA_CNT_ELECNT_OF(BUFFER_SIZE*11)
> > ),
> >
> > /* DST Setup */
> > EDMA_DST_RMK(MCBSP_getXmtAddr(hMcbsp1)),
> >
> > /* IDX Setup */
> > EDMA_IDX_RMK(0,0),
> >
> > /* RLD Setup */
> > EDMA_RLD_RMK(0,0)
> > );
> >
> > EDMA_configArgs(hEdma15,
> >
> > /* OPT Setup */
> >
> > EDMA_OPT_RMK(
> > EDMA_OPT_PRI_HIGH, /* 1 */
> > EDMA_OPT_ESIZE_16BIT, /* 01 */
> > EDMA_OPT_2DS_NO, /* 0 */
> > EDMA_OPT_SUM_NONE, /* 00 */
> > EDMA_OPT_2DD_NO, /* 0 */
> > EDMA_OPT_DUM_INC, /* 01 */
> > EDMA_OPT_TCINT_YES, /* 1 */
> > EDMA_OPT_TCC_OF(15), /* 15 */
> > EDMA_OPT_LINK_NO, /* 0 */
> > EDMA_OPT_FS_NO /* 0 */
> > ),
> >
> > /* SRC Setup */
> > EDMA_SRC_RMK(MCBSP_getRcvAddr(hMcbsp1)),
> >
> > /* CNT Setup */
> > EDMA_CNT_RMK(0, (BUFFER_SIZE * 11)),
> >
> > /* DST Setup */
> > EDMA_DST_RMK((Uint32) recvbuf), /*recvbuf address*/
> >
> > /* IDX Setup */
> > EDMA_IDX_RMK(0,0),
> >
> > /* RLD Setup */
> > EDMA_RLD_RMK(0,0)
> > );
> >
> > } /* End of ConfigEDMA() */
> >
> > *******************************************************************/
> > /* void ConfigMcBSP(void): Setup for McBSP Configuration */
> > /*******************************************************************/
> > void ConfigMcBSP(void)
> > {
> >
> > MCBSP_Config mcbspCfg1 = {
> >
> > /* SPCR Setup */
> > MCBSP_SPCR_RMK(
> > MCBSP_SPCR_FREE_YES, /* 1 */
> > MCBSP_SPCR_SOFT_DEFAULT, /* 0 */
> > MCBSP_SPCR_FRST_DEFAULT, /* 0 */
> > MCBSP_SPCR_GRST_DEFAULT, /* 0 */
> > MCBSP_SPCR_XINTM_XRDY, /* 00 */
> > MCBSP_SPCR_XSYNCERR_DEFAULT, /* 0 */
> > MCBSP_SPCR_XRST_DEFAULT, /* 0 */
> > MCBSP_SPCR_DLB_OFF, /* 0 */
> > MCBSP_SPCR_RJUST_RZF, /* 00 */
> > MCBSP_SPCR_CLKSTP_DISABLE, /* 0 */
> > MCBSP_SPCR_DXENA_OFF, /* 0 */
> > MCBSP_SPCR_RINTM_RRDY, /* 00 */
> > MCBSP_SPCR_RSYNCERR_DEFAULT, /* 0 */
> > MCBSP_SPCR_RRST_DEFAULT /* 0 */
> > ),
> >
> > /* RCR Setup */
> > MCBSP_RCR_RMK(
> > MCBSP_RCR_RPHASE_DUAL, /* 1 */
> > MCBSP_RCR_RFRLEN2_OF(1), /* 00010 */
> > MCBSP_RCR_RWDLEN2_8BIT, /* 000 */
> > MCBSP_RCR_RCOMPAND_MSB, /* 00 */
> > MCBSP_RCR_RFIG_YES, /* 1 */
> > MCBSP_RCR_RDATDLY_1BIT, /* 01 */
> > MCBSP_RCR_RFRLEN1_OF(8), /* 01000 */
> > MCBSP_RCR_RWDLEN1_16BIT, /* 010 */
> > MCBSP_RCR_RWDREVRS_DISABLE /* 0 */
> > ),
> >
> > /* XCR Setup */
> >
> > MCBSP_XCR_RMK(
> > MCBSP_XCR_XPHASE_DUAL, /* 1 */
> > MCBSP_XCR_XFRLEN2_OF(1), /* 00010 */
> > MCBSP_XCR_XWDLEN2_8BIT, /* 000 */
> > MCBSP_XCR_XCOMPAND_MSB, /* 00 */
> > MCBSP_XCR_XFIG_YES, /* 1 */
> > MCBSP_XCR_XDATDLY_0BIT, /* 00 */
> > MCBSP_XCR_XFRLEN1_OF(8), /* 01000 */
> > MCBSP_XCR_XWDLEN1_16BIT, /* 010 */
> > MCBSP_XCR_XWDREVRS_DISABLE /* 0 */
> > ),
> > #endif
> >
> > /* SRGR Setup */
> > MCBSP_SRGR_RMK(
> > MCBSP_SRGR_GSYNC_FREE, /* 0 */
> > MCBSP_SRGR_CLKSP_RISING, /* 0*/
> > MCBSP_SRGR_CLKSM_INTERNAL, /* 1 */
> > MCBSP_SRGR_FSGM_DXR2XSR, /* 0 */
> > MCBSP_SRGR_FPER_DEFAULT, /* 0 */
> > MCBSP_SRGR_FWID_DEFAULT, /* 0 */
> > MCBSP_SRGR_CLKGDV_OF(732) /* CLKGDV */
> >
> > ),
> >
> > /* MCR Setup */
> > MCBSP_MCR_DEFAULT,
> > /* RCER Setup */
> > MCBSP_RCER_DEFAULT,
> >
> > /* XCER Setup */
> > MCBSP_XCER_DEFAULT,
> >
> > /* PCR Setup */
> > MCBSP_PCR_RMK(
> > MCBSP_PCR_XIOEN_SP, /* 0 */
> > MCBSP_PCR_RIOEN_SP, /* 0 */
> > MCBSP_PCR_FSXM_INTERNAL, /* 1 */
> > MCBSP_PCR_FSRM_EXTERNAL, /* 0 */
> > MCBSP_PCR_CLKXM_OUTPUT, /* 1 */
> > MCBSP_PCR_CLKRM_OUTPUT, /* 1 */
> > MCBSP_PCR_CLKSSTAT_0, /* 0 */
> > MCBSP_PCR_DXSTAT_0, /* 0 */
> > MCBSP_PCR_FSXP_ACTIVELOW, /* 1 */
> > MCBSP_PCR_FSRP_ACTIVELOW, /* 1 */
> > MCBSP_PCR_CLKXP_RISING, /* 0 */
> > MCBSP_PCR_CLKRP_FALLING /* 0 */
> > )
> > };
> >
> > MCBSP_config(hMcbsp1, &mcbspCfg1);
> >
> > } /* end of Config_McBSP(void) */
> >
> > And as for "Did you implement the part about replacing every bit to xmit'd with 4 occurrances of that bit?
> >
> > Did you implement the part about using a 'majority rules' to extract each bit from the recv'd bit stream?" . Though the logic used is this , but j had not chked it, as until and unless the recvbuf data is correcct and equal to xmitbuf data,how will this logic be correct???
> >
> >
> ------- End of Original Message -------
> --
> AVINASH JHA
>
> Attachment(s) from avinash jha
> 1 of 1 File(s)
>
> tek0001ALL.csv Start a New Thread

Yes,i myself chkd it nd there was an error,just aftr i sent u the
mail,i chkd the xmitbuf nd all d data there were 0.I corrected it nd
wl send u the new data wid graph nd snapshots nxt tym.

On 4/23/10, Richard Williams wrote:
> Avin,
>
> I looked through the data you sent.
> all 10000 rows.
> Then I plotted the data into a chart with several different views.
>
> There is NO valid data of any outputs from the signals produced by the McBSP
> in any of those rows.
>
> All the time is near 0, which may be acceptable.
> All the voltages are near 0 which is not acceptable.
>
> Is this just an error in the selection of the data or is it characteristic.
>
> If this data is characteristic, then the source code is a long ways from
> being correct as no McBSP output is being produced.
>
> R. Williams
>
> ---------- Original Message -----------
> From: avinash jha
> To: Richard Williams
> Cc: c...
> Sent: Fri, 23 Apr 2010 17:19:07 +0530
> Subject: Re: [c6x] Re: UART on DSK6713 [1 Attachment]
>
>> [Attachment(s) from avinash jha included below]
>>
>> the data from logic analyzer.
>>
>> channel had DXR pin, cahnnel 2 had FSX pin, Channnel 3 had DRR pin.
>> chk plz.
>>
>> On 4/22/10, Richard Williams wrote:
>> Avin,
>>
>> do you have a logic analyzer, I think you stated that you do?
>> If so, it is very simple..
>> connect the trigger lead from the logic analyzer to the FSX pin of the
>> DSP.
>> connect a data lead from the logic analyzer to the DX pin of the DSP.
>> Save the result as a file. (to a floppy)
>> attach that file to your post.
>>
>> For completeness, you may also want to capture the CLKX signal line with
>> the logic analyzer.
>>
>> You may also want to experiment with the info at:
>> 2.5.5.7 32-Bit Bit Reversal: RWDREVRS, XWDREVRS in SPRUGJ6C to see if you
>> can fix the data reversal problem.
>>
>> R. Williams
>>
>> ---------- Original Message -----------
>> From: a...@gmail.com
>> To: c...
>> Sent: Thu, 22 Apr 2010 00:39:41 -0400
>> Subject: [c6x] Re: UART on DSK6713
>>
>> >
>> >
>>
>> > k..No i haven't checked the DXR line for what is being transmitted.I
>> > thought to do this, but how to do it?? i don't know.Plz suggest a way to
>> > chk DXR and DRR.
>> >
>> > As for McBSP clock, i have set CLKGDV according to the formula in
>> > spra633, i.e. (CPU freq)/(baud rate*16)-1.As per this one, CPU frequency
>> > of 6713 is 225MHZ, Baud rate i keep 19,200, so CLKGDV comes 731
>> > approx.Do i need to set any other CLK??? which one???
>> >
>> > Here I am posting the configuration part of McBSP and EDMA which has the
>> > information regarding, MSB or LSB and CLKGDV.
>> >
>> > /*******************************************************************/
>> > /* void ConfigEDMA(void): set up EDMA channel 14/15 for UART Xmit */
>> > /*******************************************************************/
>> > void ConfigEDMA(void)
>> > {
>> > EDMA_configArgs(hEdma14,
>> >
>> > /* OPT Setup */
>> > EDMA_OPT_RMK(
>> > EDMA_OPT_PRI_HIGH, /* 1 */
>> > EDMA_OPT_ESIZE_16BIT, /* 01 */
>> > EDMA_OPT_2DS_NO, /* 0 */
>> > EDMA_OPT_SUM_INC, /* 01 */
>> > EDMA_OPT_2DD_NO, /* 0 */
>> > EDMA_OPT_DUM_NONE, /* 00 */
>> > EDMA_OPT_TCINT_YES, /* 1 */
>> > EDMA_OPT_TCC_OF(14), /* 14 */
>> > EDMA_OPT_LINK_NO, /* 0 */
>> > EDMA_OPT_FS_NO /* 0 */
>> > ),
>> >
>> > /* SRC Setup */
>> > EDMA_SRC_RMK((Uint32) xmitbuf), /*xmitbuf address*/
>> >
>> > /* CNT Setup */
>> > EDMA_CNT_RMK(
>> > EDMA_CNT_FRMCNT_DEFAULT,
>> > EDMA_CNT_ELECNT_OF(BUFFER_SIZE*11)
>> > ),
>> >
>> > /* DST Setup */
>> > EDMA_DST_RMK(MCBSP_getXmtAddr(hMcbsp1)),
>> >
>> > /* IDX Setup */
>> > EDMA_IDX_RMK(0,0),
>> >
>> > /* RLD Setup */
>> > EDMA_RLD_RMK(0,0)
>> > );
>> >
>> > EDMA_configArgs(hEdma15,
>> >
>> > /* OPT Setup */
>> >
>> > EDMA_OPT_RMK(
>> > EDMA_OPT_PRI_HIGH, /* 1 */
>> > EDMA_OPT_ESIZE_16BIT, /* 01 */
>> > EDMA_OPT_2DS_NO, /* 0 */
>> > EDMA_OPT_SUM_NONE, /* 00 */
>> > EDMA_OPT_2DD_NO, /* 0 */
>> > EDMA_OPT_DUM_INC, /* 01 */
>> > EDMA_OPT_TCINT_YES, /* 1 */
>> > EDMA_OPT_TCC_OF(15), /* 15 */
>> > EDMA_OPT_LINK_NO, /* 0 */
>> > EDMA_OPT_FS_NO /* 0 */
>> > ),
>> >
>> > /* SRC Setup */
>> > EDMA_SRC_RMK(MCBSP_getRcvAddr(hMcbsp1)),
>> >
>> > /* CNT Setup */
>> > EDMA_CNT_RMK(0, (BUFFER_SIZE * 11)),
>> >
>> > /* DST Setup */
>> > EDMA_DST_RMK((Uint32) recvbuf), /*recvbuf address*/
>> >
>> > /* IDX Setup */
>> > EDMA_IDX_RMK(0,0),
>> >
>> > /* RLD Setup */
>> > EDMA_RLD_RMK(0,0)
>> > );
>> >
>> > } /* End of ConfigEDMA() */
>> >
>> > *******************************************************************/
>> > /* void ConfigMcBSP(void): Setup for McBSP Configuration */
>> > /*******************************************************************/
>> > void ConfigMcBSP(void)
>> > {
>> >
>> > MCBSP_Config mcbspCfg1 = {
>> >
>> > /* SPCR Setup */
>> > MCBSP_SPCR_RMK(
>> > MCBSP_SPCR_FREE_YES, /* 1 */
>> > MCBSP_SPCR_SOFT_DEFAULT, /* 0 */
>> > MCBSP_SPCR_FRST_DEFAULT, /* 0 */
>> > MCBSP_SPCR_GRST_DEFAULT, /* 0 */
>> > MCBSP_SPCR_XINTM_XRDY, /* 00 */
>> > MCBSP_SPCR_XSYNCERR_DEFAULT, /* 0 */
>> > MCBSP_SPCR_XRST_DEFAULT, /* 0 */
>> > MCBSP_SPCR_DLB_OFF, /* 0 */
>> > MCBSP_SPCR_RJUST_RZF, /* 00 */
>> > MCBSP_SPCR_CLKSTP_DISABLE, /* 0 */
>> > MCBSP_SPCR_DXENA_OFF, /* 0 */
>> > MCBSP_SPCR_RINTM_RRDY, /* 00 */
>> > MCBSP_SPCR_RSYNCERR_DEFAULT, /* 0 */
>> > MCBSP_SPCR_RRST_DEFAULT /* 0 */
>> > ),
>> >
>> > /* RCR Setup */
>> > MCBSP_RCR_RMK(
>> > MCBSP_RCR_RPHASE_DUAL, /* 1 */
>> > MCBSP_RCR_RFRLEN2_OF(1), /* 00010 */
>> > MCBSP_RCR_RWDLEN2_8BIT, /* 000 */
>> > MCBSP_RCR_RCOMPAND_MSB, /* 00 */
>> > MCBSP_RCR_RFIG_YES, /* 1 */
>> > MCBSP_RCR_RDATDLY_1BIT, /* 01 */
>> > MCBSP_RCR_RFRLEN1_OF(8), /* 01000 */
>> > MCBSP_RCR_RWDLEN1_16BIT, /* 010 */
>> > MCBSP_RCR_RWDREVRS_DISABLE /* 0 */
>> > ),
>> >
>> > /* XCR Setup */
>> >
>> > MCBSP_XCR_RMK(
>> > MCBSP_XCR_XPHASE_DUAL, /* 1 */
>> > MCBSP_XCR_XFRLEN2_OF(1), /* 00010 */
>> > MCBSP_XCR_XWDLEN2_8BIT, /* 000 */
>> > MCBSP_XCR_XCOMPAND_MSB, /* 00 */
>> > MCBSP_XCR_XFIG_YES, /* 1 */
>> > MCBSP_XCR_XDATDLY_0BIT, /* 00 */
>> > MCBSP_XCR_XFRLEN1_OF(8), /* 01000 */
>> > MCBSP_XCR_XWDLEN1_16BIT, /* 010 */
>> > MCBSP_XCR_XWDREVRS_DISABLE /* 0 */
>> > ),
>> > #endif
>> >
>> > /* SRGR Setup */
>> > MCBSP_SRGR_RMK(
>> > MCBSP_SRGR_GSYNC_FREE, /* 0 */
>> > MCBSP_SRGR_CLKSP_RISING, /* 0*/
>> > MCBSP_SRGR_CLKSM_INTERNAL, /* 1 */
>> > MCBSP_SRGR_FSGM_DXR2XSR, /* 0 */
>> > MCBSP_SRGR_FPER_DEFAULT, /* 0 */
>> > MCBSP_SRGR_FWID_DEFAULT, /* 0 */
>> > MCBSP_SRGR_CLKGDV_OF(732) /* CLKGDV */
>> >
>> > ),
>> >
>> > /* MCR Setup */
>> > MCBSP_MCR_DEFAULT,
>> > /* RCER Setup */
>> > MCBSP_RCER_DEFAULT,
>> >
>> > /* XCER Setup */
>> > MCBSP_XCER_DEFAULT,
>> >
>> > /* PCR Setup */
>> > MCBSP_PCR_RMK(
>> > MCBSP_PCR_XIOEN_SP, /* 0 */
>> > MCBSP_PCR_RIOEN_SP, /* 0 */
>> > MCBSP_PCR_FSXM_INTERNAL, /* 1 */
>> > MCBSP_PCR_FSRM_EXTERNAL, /* 0 */
>> > MCBSP_PCR_CLKXM_OUTPUT, /* 1 */
>> > MCBSP_PCR_CLKRM_OUTPUT, /* 1 */
>> > MCBSP_PCR_CLKSSTAT_0, /* 0 */
>> > MCBSP_PCR_DXSTAT_0, /* 0 */
>> > MCBSP_PCR_FSXP_ACTIVELOW, /* 1 */
>> > MCBSP_PCR_FSRP_ACTIVELOW, /* 1 */
>> > MCBSP_PCR_CLKXP_RISING, /* 0 */
>> > MCBSP_PCR_CLKRP_FALLING /* 0 */
>> > )
>> > };
>> >
>> > MCBSP_config(hMcbsp1, &mcbspCfg1);
>> >
>> > } /* end of Config_McBSP(void) */
>> >
>> > And as for "Did you implement the part about replacing every bit to
>> > xmit'd with 4 occurrances of that bit?
>> >
>> > Did you implement the part about using a 'majority rules' to extract
>> > each bit from the recv'd bit stream?" . Though the logic used is this ,
>> > but j had not chked it, as until and unless the recvbuf data is correcct
>> > and equal to xmitbuf data,how will this logic be correct???
>> >
>> >
>> ------- End of Original Message -------
>> --
>> AVINASH JHA
>>
>> Attachment(s) from avinash jha
>> 1 of 1 File(s)
>>
>> tek0001ALL.csv
>
--
AVINASH JHA

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