Hello,
I am using the C6416T DSK to interface to an FPGA which is in turn
interfaced to an ADC ( ADS 5485 ; 200 MSPS ; 16 bit ).
I found that there is an ECLKIN pin on the EMIF datasheet and that the EMIFA
can be externally clocked from an FPGA. But when I checked out the pins on
the J4 memory expansion slot I couldn't find the ELCKIN. So
1. Is there a way to externally clock the EMIF or
2. Does the FPGA need the clock from the EMIF's clock out ( ECLKOUT
located
on the PCI connector ) ??
Regards,
--
Varun
TMS320C64X DSK's EMIF
Started by ●May 20, 2010
Reply by ●May 20, 20102010-05-20
Varun,
On Thu, May 20, 2010 at 1:10 AM, varoonian . wrote:
> Hello,
>
> I am using the C6416T DSK to interface to an FPGA which is in turn
> interfaced to an ADC ( ADS 5485 ; 200 MSPS ; 16 bit ).
>
> I found that there is an ECLKIN pin on the EMIF datasheet and that the
> EMIFA can be externally clocked from an FPGA. But when I checked out the
> pins on the J4 memory expansion slot I couldn't find the ELCKIN. So
>
> 1. Is there a way to externally clock the EMIF or
>
The DC interface was designed many years ago for the first c6x DSP [6201].
It does not support external EMIF clocking.
> 2. Does the FPGA need the clock from the EMIF's clock out ( ECLKOUT located
> on the PCI connector ) ??
>
I think that you can use the clkout on the second DC connector.
The second problem that you will face is that only 32 data pins are brought
out to the DC connector [all 64 would double the IO bandwidth. To increase
the performance, you will need to transfer 32 bits at a time to reduce the
number of xfers by 1/2.
I do not know the details of your project, but if you are going to sample
the data at 2x the frequency that you need, you might consider putting some
logic in the FPGA to resolve the 2 samples to a single value to again reduce
the number of IO xfers by 1/2.
mikedunn
>
> Regards,
>
> --
> Varun
>
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
On Thu, May 20, 2010 at 1:10 AM, varoonian . wrote:
> Hello,
>
> I am using the C6416T DSK to interface to an FPGA which is in turn
> interfaced to an ADC ( ADS 5485 ; 200 MSPS ; 16 bit ).
>
> I found that there is an ECLKIN pin on the EMIF datasheet and that the
> EMIFA can be externally clocked from an FPGA. But when I checked out the
> pins on the J4 memory expansion slot I couldn't find the ELCKIN. So
>
> 1. Is there a way to externally clock the EMIF or
>
The DC interface was designed many years ago for the first c6x DSP [6201].
It does not support external EMIF clocking.
> 2. Does the FPGA need the clock from the EMIF's clock out ( ECLKOUT located
> on the PCI connector ) ??
>
I think that you can use the clkout on the second DC connector.
The second problem that you will face is that only 32 data pins are brought
out to the DC connector [all 64 would double the IO bandwidth. To increase
the performance, you will need to transfer 32 bits at a time to reduce the
number of xfers by 1/2.
I do not know the details of your project, but if you are going to sample
the data at 2x the frequency that you need, you might consider putting some
logic in the FPGA to resolve the 2 samples to a single value to again reduce
the number of IO xfers by 1/2.
mikedunn
>
> Regards,
>
> --
> Varun
>
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
Reply by ●May 20, 20102010-05-20
Varun-
> I am using the C6416T DSK to interface to an FPGA which is in turn
> interfaced to an ADC ( ADS 5485 ; 200 MSPS ; 16 bit ).
>
> I found that there is an ECLKIN pin on the EMIF datasheet and that the EMIFA
> can be externally clocked from an FPGA. But when I checked out the pins on
> the J4 memory expansion slot I couldn't find the ELCKIN. So
>
> 1. Is there a way to externally clock the EMIF or
> 2. Does the FPGA need the clock from the EMIF's clock out ( ECLKOUT located
> on the PCI connector ) ??
I read your e2e thread on this:
http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/p/42770/169339.aspx
and I think you got some good answers from TI folks. The PCI connector has no EMIF-related signals; you should
definitely not try to hook up to that.
One suggestion is to study TI's eval board for the ADS 5485:
http://focus.ti.com/docs/toolsw/folders/print/ads5485evm.html
and think carefully about how TI recommends to read ADS 5485 LVDS outputs using a logic analyzer. Whatever TI is
doing there, is exactly what you want to do with your FPGA. Then inside the FPGA store samples in a FIFO, then read
the FIFO from C6416 EMIF interface (via the DSK daughtercard).
Using this approach, your EMIF interface issues (like clock) are isolated from the ADS5485, and you focus instead on
the FPGA and FIFO.
-Jeff
_____________________________________
> I am using the C6416T DSK to interface to an FPGA which is in turn
> interfaced to an ADC ( ADS 5485 ; 200 MSPS ; 16 bit ).
>
> I found that there is an ECLKIN pin on the EMIF datasheet and that the EMIFA
> can be externally clocked from an FPGA. But when I checked out the pins on
> the J4 memory expansion slot I couldn't find the ELCKIN. So
>
> 1. Is there a way to externally clock the EMIF or
> 2. Does the FPGA need the clock from the EMIF's clock out ( ECLKOUT located
> on the PCI connector ) ??
I read your e2e thread on this:
http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/p/42770/169339.aspx
and I think you got some good answers from TI folks. The PCI connector has no EMIF-related signals; you should
definitely not try to hook up to that.
One suggestion is to study TI's eval board for the ADS 5485:
http://focus.ti.com/docs/toolsw/folders/print/ads5485evm.html
and think carefully about how TI recommends to read ADS 5485 LVDS outputs using a logic analyzer. Whatever TI is
doing there, is exactly what you want to do with your FPGA. Then inside the FPGA store samples in a FIFO, then read
the FIFO from C6416 EMIF interface (via the DSK daughtercard).
Using this approach, your EMIF interface issues (like clock) are isolated from the ADS5485, and you focus instead on
the FPGA and FIFO.
-Jeff
_____________________________________
Reply by ●May 21, 20102010-05-21
Varun-
> Yes you are right. I posted the same question on *TI's E2E forum.
>
> *I figured out not to connect the PCI to the FPGA. That's taken care of. We
> have also decided to use an FPGA between the ADC and the DSK. Thanks for the
> link on the ADC 5485 EVM. I will look into it and post again.
Ok.
-Jeff
> On Thu, May 20, 2010 at 3:58 PM, Jeff Brower wrote:
>
>> Varun-
>>
>> > I am using the C6416T DSK to interface to an FPGA which is in turn
>> > interfaced to an ADC ( ADS 5485 ; 200 MSPS ; 16 bit ).
>> >
>> > I found that there is an ECLKIN pin on the EMIF datasheet and that the
>> EMIFA
>> > can be externally clocked from an FPGA. But when I checked out the pins
>> on
>> > the J4 memory expansion slot I couldn't find the ELCKIN. So
>> >
>> > 1. Is there a way to externally clock the EMIF or
>> > 2. Does the FPGA need the clock from the EMIF's clock out ( ECLKOUT
>> located
>> > on the PCI connector ) ??
>>
>> I read your e2e thread on this:
>> http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/p/42770/169339.aspx
>>
>> and I think you got some good answers from TI folks. The PCI connector has
>> no EMIF-related signals; you should
>> definitely not try to hook up to that.
>>
>> One suggestion is to study TI's eval board for the ADS 5485:
>>
>> http://focus.ti.com/docs/toolsw/folders/print/ads5485evm.html
>>
>> and think carefully about how TI recommends to read ADS 5485 LVDS outputs
>> using a logic analyzer. Whatever TI is
>> doing there, is exactly what you want to do with your FPGA. Then inside
>> the FPGA store samples in a FIFO, then read
>> the FIFO from C6416 EMIF interface (via the DSK daughtercard).
>>
>> Using this approach, your EMIF interface issues (like clock) are isolated
>> from the ADS5485, and you focus instead on
>> the FPGA and FIFO.
>>
>> -Jeff
> --
> Varun
_____________________________________
> Yes you are right. I posted the same question on *TI's E2E forum.
>
> *I figured out not to connect the PCI to the FPGA. That's taken care of. We
> have also decided to use an FPGA between the ADC and the DSK. Thanks for the
> link on the ADC 5485 EVM. I will look into it and post again.
Ok.
-Jeff
> On Thu, May 20, 2010 at 3:58 PM, Jeff Brower wrote:
>
>> Varun-
>>
>> > I am using the C6416T DSK to interface to an FPGA which is in turn
>> > interfaced to an ADC ( ADS 5485 ; 200 MSPS ; 16 bit ).
>> >
>> > I found that there is an ECLKIN pin on the EMIF datasheet and that the
>> EMIFA
>> > can be externally clocked from an FPGA. But when I checked out the pins
>> on
>> > the J4 memory expansion slot I couldn't find the ELCKIN. So
>> >
>> > 1. Is there a way to externally clock the EMIF or
>> > 2. Does the FPGA need the clock from the EMIF's clock out ( ECLKOUT
>> located
>> > on the PCI connector ) ??
>>
>> I read your e2e thread on this:
>> http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/p/42770/169339.aspx
>>
>> and I think you got some good answers from TI folks. The PCI connector has
>> no EMIF-related signals; you should
>> definitely not try to hook up to that.
>>
>> One suggestion is to study TI's eval board for the ADS 5485:
>>
>> http://focus.ti.com/docs/toolsw/folders/print/ads5485evm.html
>>
>> and think carefully about how TI recommends to read ADS 5485 LVDS outputs
>> using a logic analyzer. Whatever TI is
>> doing there, is exactly what you want to do with your FPGA. Then inside
>> the FPGA store samples in a FIFO, then read
>> the FIFO from C6416 EMIF interface (via the DSK daughtercard).
>>
>> Using this approach, your EMIF interface issues (like clock) are isolated
>> from the ADS5485, and you focus instead on
>> the FPGA and FIFO.
>>
>> -Jeff
> --
> Varun
_____________________________________
Reply by ●May 21, 20102010-05-21
Hello Jeff,
Yes you are right. I posted the same question on *TI's E2E forum.
*I figured out not to connect the PCI to the FPGA. That's taken care of. We
have also decided to use an FPGA between the ADC and the DSK. Thanks for the
link on the ADC 5485 EVM. I will look into it and post again.
Thanks,
Varun
On Thu, May 20, 2010 at 3:58 PM, Jeff Brower wrote:
> Varun-
>
> > I am using the C6416T DSK to interface to an FPGA which is in turn
> > interfaced to an ADC ( ADS 5485 ; 200 MSPS ; 16 bit ).
> >
> > I found that there is an ECLKIN pin on the EMIF datasheet and that the
> EMIFA
> > can be externally clocked from an FPGA. But when I checked out the pins
> on
> > the J4 memory expansion slot I couldn't find the ELCKIN. So
> >
> > 1. Is there a way to externally clock the EMIF or
> > 2. Does the FPGA need the clock from the EMIF's clock out ( ECLKOUT
> located
> > on the PCI connector ) ??
>
> I read your e2e thread on this:
> http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/p/42770/169339.aspx
>
> and I think you got some good answers from TI folks. The PCI connector has
> no EMIF-related signals; you should
> definitely not try to hook up to that.
>
> One suggestion is to study TI's eval board for the ADS 5485:
>
> http://focus.ti.com/docs/toolsw/folders/print/ads5485evm.html
>
> and think carefully about how TI recommends to read ADS 5485 LVDS outputs
> using a logic analyzer. Whatever TI is
> doing there, is exactly what you want to do with your FPGA. Then inside
> the FPGA store samples in a FIFO, then read
> the FIFO from C6416 EMIF interface (via the DSK daughtercard).
>
> Using this approach, your EMIF interface issues (like clock) are isolated
> from the ADS5485, and you focus instead on
> the FPGA and FIFO.
>
> -Jeff
--
Varun
Yes you are right. I posted the same question on *TI's E2E forum.
*I figured out not to connect the PCI to the FPGA. That's taken care of. We
have also decided to use an FPGA between the ADC and the DSK. Thanks for the
link on the ADC 5485 EVM. I will look into it and post again.
Thanks,
Varun
On Thu, May 20, 2010 at 3:58 PM, Jeff Brower wrote:
> Varun-
>
> > I am using the C6416T DSK to interface to an FPGA which is in turn
> > interfaced to an ADC ( ADS 5485 ; 200 MSPS ; 16 bit ).
> >
> > I found that there is an ECLKIN pin on the EMIF datasheet and that the
> EMIFA
> > can be externally clocked from an FPGA. But when I checked out the pins
> on
> > the J4 memory expansion slot I couldn't find the ELCKIN. So
> >
> > 1. Is there a way to externally clock the EMIF or
> > 2. Does the FPGA need the clock from the EMIF's clock out ( ECLKOUT
> located
> > on the PCI connector ) ??
>
> I read your e2e thread on this:
> http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/p/42770/169339.aspx
>
> and I think you got some good answers from TI folks. The PCI connector has
> no EMIF-related signals; you should
> definitely not try to hook up to that.
>
> One suggestion is to study TI's eval board for the ADS 5485:
>
> http://focus.ti.com/docs/toolsw/folders/print/ads5485evm.html
>
> and think carefully about how TI recommends to read ADS 5485 LVDS outputs
> using a logic analyzer. Whatever TI is
> doing there, is exactly what you want to do with your FPGA. Then inside
> the FPGA store samples in a FIFO, then read
> the FIFO from C6416 EMIF interface (via the DSK daughtercard).
>
> Using this approach, your EMIF interface issues (like clock) are isolated
> from the ADS5485, and you focus instead on
> the FPGA and FIFO.
>
> -Jeff
--
Varun
