Hello,
I need to connect the TMS320"6416" DSK to the Virtex-5 FPGA.
In order to do that I need to know the *IO functionalites of the DSK. *
**Can anyone kindly suggest any manuals or documents to go about before
programming the EMIF on the DSK. Programming examples will be of great help
to me.
Do I also need to learn about GPIO ??
Thanks,
--
Varun
EMIF Programming
Started by ●July 7, 2010
Reply by ●July 8, 20102010-07-08
Dear Mr.Dunn,
Thank you very much.
I will be using the DDR RAM ( 256 MB ) on the Virtex-5 Board since the SDRAM
of 16 MB on the DSK isn't sufficient.
But I notice the EMIFA has only 22 address lines, which means I'll be able
to access only 2^22 = approx (4MB) of external memory. How does one deal
with this kind of problem ?
Thanks,
On Wed, Jul 7, 2010 at 6:38 PM, Michael Dunn wrote:
> Varun,
>
> On Wed, Jul 7, 2010 at 1:49 AM, varoonian . wrote:
>
>> Hello,
>>
>> I need to connect the TMS320"6416" DSK to the Virtex-5 FPGA.
>>
>> In order to do that I need to know the *IO functionalites of the DSK. *
>>
>
> If you are interested in performance and flexibility, I suggest that you
> configure your FPGA as a memory mapped device [all access is by reading and
> writing memory locations]. You don't need to worry about any other 'I/O'
> capabilities. If you can afford it, use a 32 bit data interface [as opposed
> to 16 or 8 bits].
>> **Can anyone kindly suggest any manuals or documents to go about before
>> programming the EMIF on the DSK. Programming examples will be of great help
>> to me.
>>
>
> The only EMIF programming that you will need to do is a one time setup.
> Review the EMIF setup in the DSK GEL file - you may be able to use them 'as
> is' or you might have to change 1 value for your application.
> Check spru190.pdf and look up the 'spru' number for the EMIF manual.
>
>>
>> Do I also need to learn about GPIO ??
>>
>
> no.
>
> mikedunn
>
>>
>> Thanks,
>>
>> --
>> Varun
>>
>> --
> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>
--
Varun
Thank you very much.
I will be using the DDR RAM ( 256 MB ) on the Virtex-5 Board since the SDRAM
of 16 MB on the DSK isn't sufficient.
But I notice the EMIFA has only 22 address lines, which means I'll be able
to access only 2^22 = approx (4MB) of external memory. How does one deal
with this kind of problem ?
Thanks,
On Wed, Jul 7, 2010 at 6:38 PM, Michael Dunn wrote:
> Varun,
>
> On Wed, Jul 7, 2010 at 1:49 AM, varoonian . wrote:
>
>> Hello,
>>
>> I need to connect the TMS320"6416" DSK to the Virtex-5 FPGA.
>>
>> In order to do that I need to know the *IO functionalites of the DSK. *
>>
>
> If you are interested in performance and flexibility, I suggest that you
> configure your FPGA as a memory mapped device [all access is by reading and
> writing memory locations]. You don't need to worry about any other 'I/O'
> capabilities. If you can afford it, use a 32 bit data interface [as opposed
> to 16 or 8 bits].
>> **Can anyone kindly suggest any manuals or documents to go about before
>> programming the EMIF on the DSK. Programming examples will be of great help
>> to me.
>>
>
> The only EMIF programming that you will need to do is a one time setup.
> Review the EMIF setup in the DSK GEL file - you may be able to use them 'as
> is' or you might have to change 1 value for your application.
> Check spru190.pdf and look up the 'spru' number for the EMIF manual.
>
>>
>> Do I also need to learn about GPIO ??
>>
>
> no.
>
> mikedunn
>
>>
>> Thanks,
>>
>> --
>> Varun
>>
>> --
> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>
--
Varun
Reply by ●July 8, 20102010-07-08
Varun,
On Wed, Jul 7, 2010 at 1:49 AM, varoonian . wrote:
> Hello,
>
> I need to connect the TMS320"6416" DSK to the Virtex-5 FPGA.
>
> In order to do that I need to know the *IO functionalites of the DSK. *
>
If you are interested in performance and flexibility, I suggest that you
configure your FPGA as a memory mapped device [all access is by reading and
writing memory locations]. You don't need to worry about any other 'I/O'
capabilities. If you can afford it, use a 32 bit data interface [as opposed
to 16 or 8 bits].
> **Can anyone kindly suggest any manuals or documents to go about before
> programming the EMIF on the DSK. Programming examples will be of great help
> to me.
>
The only EMIF programming that you will need to do is a one time setup.
Review the EMIF setup in the DSK GEL file - you may be able to use them 'as
is' or you might have to change 1 value for your application.
Check spru190.pdf and look up the 'spru' number for the EMIF manual.
>
> Do I also need to learn about GPIO ??
>
no.
mikedunn
>
> Thanks,
>
> --
> Varun
>
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
On Wed, Jul 7, 2010 at 1:49 AM, varoonian . wrote:
> Hello,
>
> I need to connect the TMS320"6416" DSK to the Virtex-5 FPGA.
>
> In order to do that I need to know the *IO functionalites of the DSK. *
>
If you are interested in performance and flexibility, I suggest that you
configure your FPGA as a memory mapped device [all access is by reading and
writing memory locations]. You don't need to worry about any other 'I/O'
capabilities. If you can afford it, use a 32 bit data interface [as opposed
to 16 or 8 bits].
> **Can anyone kindly suggest any manuals or documents to go about before
> programming the EMIF on the DSK. Programming examples will be of great help
> to me.
>
The only EMIF programming that you will need to do is a one time setup.
Review the EMIF setup in the DSK GEL file - you may be able to use them 'as
is' or you might have to change 1 value for your application.
Check spru190.pdf and look up the 'spru' number for the EMIF manual.
>
> Do I also need to learn about GPIO ??
>
no.
mikedunn
>
> Thanks,
>
> --
> Varun
>
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
Reply by ●July 8, 20102010-07-08
Varun,
On Thu, Jul 8, 2010 at 12:42 AM, varoonian . wrote:
> Dear Mr.Dunn,
>
> Thank you very much.
>
> I will be using the DDR RAM ( 256 MB ) on the Virtex-5 Board since the
> SDRAM of 16 MB on the DSK isn't sufficient.
>
You may want to use the 16 MB for code/data that requires more frequent
access
I am assuming that the Virtex-5 Board will be accessed by
6416_EMIF_async->DCIF_>Virtex_MemController->DDR_RAM.
I anticipate that this will be a much slower access path.
>
> But I notice the EMIFA has only 22 address lines, which means I'll be able
> to access only 2^22 = approx (4MB) of external memory. How does one deal
> with this kind of problem ?
>
Actually the device EMIFA can access 2^22 64bit locations [refer to 'byte
enables'].
Some thoughts are:
Divide the memory into 8 segments and use the existing DC interface signals
[128MB].
CE2 & !DB_CNTL0 & !DB_CNTL1 = MemSpace0 [16MB ea]
CE2 & !DB_CNTL0 & DB_CNTL1 = MemSpace1
CE2 & DB_CNTL0 & !DB_CNTL1 = MemSpace2
CE2 & DB_CNTL0 & DB_CNTL1 = MemSpace3
CE3 & !DB_CNTL0 & !DB_CNTL1 = MemSpace4
CE3 & !DB_CNTL0 & DB_CNTL1 = MemSpace5
CE3 & DB_CNTL0 & !DB_CNTL1 = MemSpace6
CE3 & DB_CNTL0 & DB_CNTL1 = MemSpace7
Always access 16MB memory 'windows' via CE2.
Define a single register in CE3 space that defines the high order address
bits [which effectively defines where the memory window is in the address
space.
!!NOTE!!:
Any of these solutions will require some special handling in software.
If your application is dealing with large data sets, keep the data separate
from the code and ensure that each data set/buffer is contained within a
single memory segment/window.
Follow the same guidelines for your code by not letting it cross
segment/window boundaries.
mikedunn
>
> Thanks,
>
> On Wed, Jul 7, 2010 at 6:38 PM, Michael Dunn wrote:
>
>> Varun,
>>
>> On Wed, Jul 7, 2010 at 1:49 AM, varoonian . wrote:
>>
>>>
>>>
>>> Hello,
>>>
>>> I need to connect the TMS320"6416" DSK to the Virtex-5 FPGA.
>>>
>>> In order to do that I need to know the *IO functionalites of the DSK. *
>>>
>>
>> If you are interested in performance and flexibility, I suggest that you
>> configure your FPGA as a memory mapped device [all access is by reading and
>> writing memory locations]. You don't need to worry about any other 'I/O'
>> capabilities. If you can afford it, use a 32 bit data interface [as opposed
>> to 16 or 8 bits].
>>> **Can anyone kindly suggest any manuals or documents to go about before
>>> programming the EMIF on the DSK. Programming examples will be of great help
>>> to me.
>>>
>>
>> The only EMIF programming that you will need to do is a one time setup.
>> Review the EMIF setup in the DSK GEL file - you may be able to use them 'as
>> is' or you might have to change 1 value for your application.
>> Check spru190.pdf and look up the 'spru' number for the EMIF manual.
>>
>>>
>>> Do I also need to learn about GPIO ??
>>>
>>
>> no.
>>
>> mikedunn
>>
>>>
>>> Thanks,
>>>
>>> --
>>> Varun
>>>
>>> --
>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>> --
> Varun
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
On Thu, Jul 8, 2010 at 12:42 AM, varoonian . wrote:
> Dear Mr.Dunn,
>
> Thank you very much.
>
> I will be using the DDR RAM ( 256 MB ) on the Virtex-5 Board since the
> SDRAM of 16 MB on the DSK isn't sufficient.
>
You may want to use the 16 MB for code/data that requires more frequent
access
I am assuming that the Virtex-5 Board will be accessed by
6416_EMIF_async->DCIF_>Virtex_MemController->DDR_RAM.
I anticipate that this will be a much slower access path.
>
> But I notice the EMIFA has only 22 address lines, which means I'll be able
> to access only 2^22 = approx (4MB) of external memory. How does one deal
> with this kind of problem ?
>
Actually the device EMIFA can access 2^22 64bit locations [refer to 'byte
enables'].
Some thoughts are:
Divide the memory into 8 segments and use the existing DC interface signals
[128MB].
CE2 & !DB_CNTL0 & !DB_CNTL1 = MemSpace0 [16MB ea]
CE2 & !DB_CNTL0 & DB_CNTL1 = MemSpace1
CE2 & DB_CNTL0 & !DB_CNTL1 = MemSpace2
CE2 & DB_CNTL0 & DB_CNTL1 = MemSpace3
CE3 & !DB_CNTL0 & !DB_CNTL1 = MemSpace4
CE3 & !DB_CNTL0 & DB_CNTL1 = MemSpace5
CE3 & DB_CNTL0 & !DB_CNTL1 = MemSpace6
CE3 & DB_CNTL0 & DB_CNTL1 = MemSpace7
Always access 16MB memory 'windows' via CE2.
Define a single register in CE3 space that defines the high order address
bits [which effectively defines where the memory window is in the address
space.
!!NOTE!!:
Any of these solutions will require some special handling in software.
If your application is dealing with large data sets, keep the data separate
from the code and ensure that each data set/buffer is contained within a
single memory segment/window.
Follow the same guidelines for your code by not letting it cross
segment/window boundaries.
mikedunn
>
> Thanks,
>
> On Wed, Jul 7, 2010 at 6:38 PM, Michael Dunn wrote:
>
>> Varun,
>>
>> On Wed, Jul 7, 2010 at 1:49 AM, varoonian . wrote:
>>
>>>
>>>
>>> Hello,
>>>
>>> I need to connect the TMS320"6416" DSK to the Virtex-5 FPGA.
>>>
>>> In order to do that I need to know the *IO functionalites of the DSK. *
>>>
>>
>> If you are interested in performance and flexibility, I suggest that you
>> configure your FPGA as a memory mapped device [all access is by reading and
>> writing memory locations]. You don't need to worry about any other 'I/O'
>> capabilities. If you can afford it, use a 32 bit data interface [as opposed
>> to 16 or 8 bits].
>>> **Can anyone kindly suggest any manuals or documents to go about before
>>> programming the EMIF on the DSK. Programming examples will be of great help
>>> to me.
>>>
>>
>> The only EMIF programming that you will need to do is a one time setup.
>> Review the EMIF setup in the DSK GEL file - you may be able to use them 'as
>> is' or you might have to change 1 value for your application.
>> Check spru190.pdf and look up the 'spru' number for the EMIF manual.
>>
>>>
>>> Do I also need to learn about GPIO ??
>>>
>>
>> no.
>>
>> mikedunn
>>
>>>
>>> Thanks,
>>>
>>> --
>>> Varun
>>>
>>> --
>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>> --
> Varun
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
Reply by ●July 10, 20102010-07-10
Thanks a lot Mr.Dunn. I'm looking into it.
Regards,
On Thu, Jul 8, 2010 at 10:06 AM, Michael Dunn wrote:
> Varun,
>
> On Thu, Jul 8, 2010 at 12:42 AM, varoonian . wrote:
>
>> Dear Mr.Dunn,
>>
>> Thank you very much.
>>
>> I will be using the DDR RAM ( 256 MB ) on the Virtex-5 Board since the
>> SDRAM of 16 MB on the DSK isn't sufficient.
>>
>
> You may want to use the 16 MB for code/data that requires more frequent
> access
> I am assuming that the Virtex-5 Board will be accessed by
> 6416_EMIF_async->DCIF_>Virtex_MemController->DDR_RAM.
> I anticipate that this will be a much slower access path.
>
>>
>> But I notice the EMIFA has only 22 address lines, which means I'll be able
>> to access only 2^22 = approx (4MB) of external memory. How does one deal
>> with this kind of problem ?
>>
>
> Actually the device EMIFA can access 2^22 64bit locations [refer to 'byte
> enables'].
> Some thoughts are:
>
> Divide the memory into 8 segments and use the existing DC interface signals
> [128MB].
> CE2 & !DB_CNTL0 & !DB_CNTL1 = MemSpace0 [16MB ea]
> CE2 & !DB_CNTL0 & DB_CNTL1 = MemSpace1
> CE2 & DB_CNTL0 & !DB_CNTL1 = MemSpace2
> CE2 & DB_CNTL0 & DB_CNTL1 = MemSpace3
> CE3 & !DB_CNTL0 & !DB_CNTL1 = MemSpace4
> CE3 & !DB_CNTL0 & DB_CNTL1 = MemSpace5
> CE3 & DB_CNTL0 & !DB_CNTL1 = MemSpace6
> CE3 & DB_CNTL0 & DB_CNTL1 = MemSpace7
>
> Always access 16MB memory 'windows' via CE2.
> Define a single register in CE3 space that defines the high order address
> bits [which effectively defines where the memory window is in the address
> space.
>
> !!NOTE!!:
> Any of these solutions will require some special handling in software.
> If your application is dealing with large data sets, keep the data separate
> from the code and ensure that each data set/buffer is contained within a
> single memory segment/window.
> Follow the same guidelines for your code by not letting it cross
> segment/window boundaries.
>
> mikedunn
>
>>
>> Thanks,
>>
>> On Wed, Jul 7, 2010 at 6:38 PM, Michael Dunn wrote:
>>
>>> Varun,
>>>
>>> On Wed, Jul 7, 2010 at 1:49 AM, varoonian . wrote:
>>>
>>>>
>>>>
>>>> Hello,
>>>>
>>>> I need to connect the TMS320"6416" DSK to the Virtex-5 FPGA.
>>>>
>>>> In order to do that I need to know the *IO functionalites of the DSK. *
>>>>
>>>
>>> If you are interested in performance and flexibility, I suggest that you
>>> configure your FPGA as a memory mapped device [all access is by reading and
>>> writing memory locations]. You don't need to worry about any other 'I/O'
>>> capabilities. If you can afford it, use a 32 bit data interface [as opposed
>>> to 16 or 8 bits].
>>>
>>>
>>>> **Can anyone kindly suggest any manuals or documents to go about
>>>> before programming the EMIF on the DSK. Programming examples will be of
>>>> great help to me.
>>>>
>>>
>>> The only EMIF programming that you will need to do is a one time setup.
>>> Review the EMIF setup in the DSK GEL file - you may be able to use them 'as
>>> is' or you might have to change 1 value for your application.
>>> Check spru190.pdf and look up the 'spru' number for the EMIF manual.
>>>
>>>>
>>>> Do I also need to learn about GPIO ??
>>>>
>>>
>>> no.
>>>
>>> mikedunn
>>>
>>>>
>>>> Thanks,
>>>>
>>>> --
>>>> Varun
>>>>
>>>>
>>>
>>>
>>>
>>> --
>>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>>> --
>> Varun
>> --
> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>
--
Varun
Regards,
On Thu, Jul 8, 2010 at 10:06 AM, Michael Dunn wrote:
> Varun,
>
> On Thu, Jul 8, 2010 at 12:42 AM, varoonian . wrote:
>
>> Dear Mr.Dunn,
>>
>> Thank you very much.
>>
>> I will be using the DDR RAM ( 256 MB ) on the Virtex-5 Board since the
>> SDRAM of 16 MB on the DSK isn't sufficient.
>>
>
> You may want to use the 16 MB for code/data that requires more frequent
> access
> I am assuming that the Virtex-5 Board will be accessed by
> 6416_EMIF_async->DCIF_>Virtex_MemController->DDR_RAM.
> I anticipate that this will be a much slower access path.
>
>>
>> But I notice the EMIFA has only 22 address lines, which means I'll be able
>> to access only 2^22 = approx (4MB) of external memory. How does one deal
>> with this kind of problem ?
>>
>
> Actually the device EMIFA can access 2^22 64bit locations [refer to 'byte
> enables'].
> Some thoughts are:
>
> Divide the memory into 8 segments and use the existing DC interface signals
> [128MB].
> CE2 & !DB_CNTL0 & !DB_CNTL1 = MemSpace0 [16MB ea]
> CE2 & !DB_CNTL0 & DB_CNTL1 = MemSpace1
> CE2 & DB_CNTL0 & !DB_CNTL1 = MemSpace2
> CE2 & DB_CNTL0 & DB_CNTL1 = MemSpace3
> CE3 & !DB_CNTL0 & !DB_CNTL1 = MemSpace4
> CE3 & !DB_CNTL0 & DB_CNTL1 = MemSpace5
> CE3 & DB_CNTL0 & !DB_CNTL1 = MemSpace6
> CE3 & DB_CNTL0 & DB_CNTL1 = MemSpace7
>
> Always access 16MB memory 'windows' via CE2.
> Define a single register in CE3 space that defines the high order address
> bits [which effectively defines where the memory window is in the address
> space.
>
> !!NOTE!!:
> Any of these solutions will require some special handling in software.
> If your application is dealing with large data sets, keep the data separate
> from the code and ensure that each data set/buffer is contained within a
> single memory segment/window.
> Follow the same guidelines for your code by not letting it cross
> segment/window boundaries.
>
> mikedunn
>
>>
>> Thanks,
>>
>> On Wed, Jul 7, 2010 at 6:38 PM, Michael Dunn wrote:
>>
>>> Varun,
>>>
>>> On Wed, Jul 7, 2010 at 1:49 AM, varoonian . wrote:
>>>
>>>>
>>>>
>>>> Hello,
>>>>
>>>> I need to connect the TMS320"6416" DSK to the Virtex-5 FPGA.
>>>>
>>>> In order to do that I need to know the *IO functionalites of the DSK. *
>>>>
>>>
>>> If you are interested in performance and flexibility, I suggest that you
>>> configure your FPGA as a memory mapped device [all access is by reading and
>>> writing memory locations]. You don't need to worry about any other 'I/O'
>>> capabilities. If you can afford it, use a 32 bit data interface [as opposed
>>> to 16 or 8 bits].
>>>
>>>
>>>> **Can anyone kindly suggest any manuals or documents to go about
>>>> before programming the EMIF on the DSK. Programming examples will be of
>>>> great help to me.
>>>>
>>>
>>> The only EMIF programming that you will need to do is a one time setup.
>>> Review the EMIF setup in the DSK GEL file - you may be able to use them 'as
>>> is' or you might have to change 1 value for your application.
>>> Check spru190.pdf and look up the 'spru' number for the EMIF manual.
>>>
>>>>
>>>> Do I also need to learn about GPIO ??
>>>>
>>>
>>> no.
>>>
>>> mikedunn
>>>
>>>>
>>>> Thanks,
>>>>
>>>> --
>>>> Varun
>>>>
>>>>
>>>
>>>
>>>
>>> --
>>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>>> --
>> Varun
>> --
> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>
--
Varun
Reply by ●July 21, 20102010-07-21
Dear Mr.Dunn,
I read about the EMIF registers and the gel file which sets the memory map
for the DSK6416.
I activated the CE0 space for SDRAM by configuring the *MTYPE* field in the
*CECTL0 register*. Is this correct ? After that initialized the SDRAM by
turning *INIT* field in the* EMIFA_SDCTL register.*
Is there a way to set the CE1space for SDRAM or Daughter Card ? .. or is it
reserved ?
For the CSL implementation is it enough if you include the necessary CSL
header file.. for example say I want to initialise the INIT bit in
SDRAM_CTL..
*#include*
*#include*
void main()
{
#define DC_REG 0x60000001
#define EMIFA_GCTL 0x01800000
#define EMIFA_CE1 0x01800004
#define EMIFA_CE0 0x01800008
#define EMIFA_CE2 0x01800010
#define EMIFA_CE3 0x01800014
#define EMIFA_SDRAMCTL 0x01800018
/* other macros as well for the rest of the EMIFA register */
*(int*)EMIFA_CE0 =0xFFFFFF33;
*(int*)EMIFA_SDRAMEXT = 0x001faf4d;
// setting INIT bit to 1 -- Initializing SDRAM //
//*(int*)EMIFA_SDRAMCTL =0x47115000;
/* CSL implemenation */
*EMIFA_SDCTL_INIT_YES;*
}
Regards,
Varun
On Sat, Jul 10, 2010 at 2:38 PM, varoonian . wrote:
> Thanks a lot Mr.Dunn. I'm looking into it.
>
> Regards,
> On Thu, Jul 8, 2010 at 10:06 AM, Michael Dunn wrote:
>
>> Varun,
>>
>> On Thu, Jul 8, 2010 at 12:42 AM, varoonian . wrote:
>>
>>> Dear Mr.Dunn,
>>>
>>> Thank you very much.
>>>
>>> I will be using the DDR RAM ( 256 MB ) on the Virtex-5 Board since the
>>> SDRAM of 16 MB on the DSK isn't sufficient.
>>>
>>
>> You may want to use the 16 MB for code/data that requires more frequent
>> access
>> I am assuming that the Virtex-5 Board will be accessed by
>> 6416_EMIF_async->DCIF_>Virtex_MemController->DDR_RAM.
>> I anticipate that this will be a much slower access path.
>>
>>>
>>> But I notice the EMIFA has only 22 address lines, which means I'll be
>>> able to access only 2^22 = approx (4MB) of external memory. How does one
>>> deal with this kind of problem ?
>>>
>>
>> Actually the device EMIFA can access 2^22 64bit locations [refer to 'byte
>> enables'].
>> Some thoughts are:
>>
>> Divide the memory into 8 segments and use the existing DC interface
>> signals [128MB].
>> CE2 & !DB_CNTL0 & !DB_CNTL1 = MemSpace0 [16MB ea]
>> CE2 & !DB_CNTL0 & DB_CNTL1 = MemSpace1
>> CE2 & DB_CNTL0 & !DB_CNTL1 = MemSpace2
>> CE2 & DB_CNTL0 & DB_CNTL1 = MemSpace3
>> CE3 & !DB_CNTL0 & !DB_CNTL1 = MemSpace4
>> CE3 & !DB_CNTL0 & DB_CNTL1 = MemSpace5
>> CE3 & DB_CNTL0 & !DB_CNTL1 = MemSpace6
>> CE3 & DB_CNTL0 & DB_CNTL1 = MemSpace7
>>
>> Always access 16MB memory 'windows' via CE2.
>> Define a single register in CE3 space that defines the high order address
>> bits [which effectively defines where the memory window is in the address
>> space.
>>
>> !!NOTE!!:
>> Any of these solutions will require some special handling in software.
>> If your application is dealing with large data sets, keep the data
>> separate from the code and ensure that each data set/buffer is contained
>> within a single memory segment/window.
>> Follow the same guidelines for your code by not letting it cross
>> segment/window boundaries.
>>
>> mikedunn
>>
>>>
>>> Thanks,
>>>
>>>
>>>
>>> On Wed, Jul 7, 2010 at 6:38 PM, Michael Dunn wrote:
>>>
>>>> Varun,
>>>>
>>>> On Wed, Jul 7, 2010 at 1:49 AM, varoonian . wrote:
>>>>
>>>>>
>>>>>
>>>>> Hello,
>>>>>
>>>>> I need to connect the TMS320"6416" DSK to the Virtex-5 FPGA.
>>>>>
>>>>> In order to do that I need to know the *IO functionalites of the DSK.
>>>>> *
>>>>>
>>>>
>>>> If you are interested in performance and flexibility, I suggest that you
>>>> configure your FPGA as a memory mapped device [all access is by reading and
>>>> writing memory locations]. You don't need to worry about any other 'I/O'
>>>> capabilities. If you can afford it, use a 32 bit data interface [as opposed
>>>> to 16 or 8 bits].
>>>>
>>>>
>>>>> **Can anyone kindly suggest any manuals or documents to go about
>>>>> before programming the EMIF on the DSK. Programming examples will be of
>>>>> great help to me.
>>>>>
>>>>
>>>> The only EMIF programming that you will need to do is a one time setup.
>>>> Review the EMIF setup in the DSK GEL file - you may be able to use them 'as
>>>> is' or you might have to change 1 value for your application.
>>>> Check spru190.pdf and look up the 'spru' number for the EMIF manual.
>>>>
>>>>>
>>>>> Do I also need to learn about GPIO ??
>>>>>
>>>>
>>>> no.
>>>>
>>>> mikedunn
>>>>
>>>>>
>>>>> Thanks,
>>>>>
>>>>> --
>>>>> Varun
>>>>>
>>>>>
>>>>
>>>>
>>>>
>>>> --
>>>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>>>>
>>>
>>>
>>>
>>> --
>>> Varun
>>> --
>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>> --
> Varun
>
--
Varun
I read about the EMIF registers and the gel file which sets the memory map
for the DSK6416.
I activated the CE0 space for SDRAM by configuring the *MTYPE* field in the
*CECTL0 register*. Is this correct ? After that initialized the SDRAM by
turning *INIT* field in the* EMIFA_SDCTL register.*
Is there a way to set the CE1space for SDRAM or Daughter Card ? .. or is it
reserved ?
For the CSL implementation is it enough if you include the necessary CSL
header file.. for example say I want to initialise the INIT bit in
SDRAM_CTL..
*#include*
*#include*
void main()
{
#define DC_REG 0x60000001
#define EMIFA_GCTL 0x01800000
#define EMIFA_CE1 0x01800004
#define EMIFA_CE0 0x01800008
#define EMIFA_CE2 0x01800010
#define EMIFA_CE3 0x01800014
#define EMIFA_SDRAMCTL 0x01800018
/* other macros as well for the rest of the EMIFA register */
*(int*)EMIFA_CE0 =0xFFFFFF33;
*(int*)EMIFA_SDRAMEXT = 0x001faf4d;
// setting INIT bit to 1 -- Initializing SDRAM //
//*(int*)EMIFA_SDRAMCTL =0x47115000;
/* CSL implemenation */
*EMIFA_SDCTL_INIT_YES;*
}
Regards,
Varun
On Sat, Jul 10, 2010 at 2:38 PM, varoonian . wrote:
> Thanks a lot Mr.Dunn. I'm looking into it.
>
> Regards,
> On Thu, Jul 8, 2010 at 10:06 AM, Michael Dunn wrote:
>
>> Varun,
>>
>> On Thu, Jul 8, 2010 at 12:42 AM, varoonian . wrote:
>>
>>> Dear Mr.Dunn,
>>>
>>> Thank you very much.
>>>
>>> I will be using the DDR RAM ( 256 MB ) on the Virtex-5 Board since the
>>> SDRAM of 16 MB on the DSK isn't sufficient.
>>>
>>
>> You may want to use the 16 MB for code/data that requires more frequent
>> access
>> I am assuming that the Virtex-5 Board will be accessed by
>> 6416_EMIF_async->DCIF_>Virtex_MemController->DDR_RAM.
>> I anticipate that this will be a much slower access path.
>>
>>>
>>> But I notice the EMIFA has only 22 address lines, which means I'll be
>>> able to access only 2^22 = approx (4MB) of external memory. How does one
>>> deal with this kind of problem ?
>>>
>>
>> Actually the device EMIFA can access 2^22 64bit locations [refer to 'byte
>> enables'].
>> Some thoughts are:
>>
>> Divide the memory into 8 segments and use the existing DC interface
>> signals [128MB].
>> CE2 & !DB_CNTL0 & !DB_CNTL1 = MemSpace0 [16MB ea]
>> CE2 & !DB_CNTL0 & DB_CNTL1 = MemSpace1
>> CE2 & DB_CNTL0 & !DB_CNTL1 = MemSpace2
>> CE2 & DB_CNTL0 & DB_CNTL1 = MemSpace3
>> CE3 & !DB_CNTL0 & !DB_CNTL1 = MemSpace4
>> CE3 & !DB_CNTL0 & DB_CNTL1 = MemSpace5
>> CE3 & DB_CNTL0 & !DB_CNTL1 = MemSpace6
>> CE3 & DB_CNTL0 & DB_CNTL1 = MemSpace7
>>
>> Always access 16MB memory 'windows' via CE2.
>> Define a single register in CE3 space that defines the high order address
>> bits [which effectively defines where the memory window is in the address
>> space.
>>
>> !!NOTE!!:
>> Any of these solutions will require some special handling in software.
>> If your application is dealing with large data sets, keep the data
>> separate from the code and ensure that each data set/buffer is contained
>> within a single memory segment/window.
>> Follow the same guidelines for your code by not letting it cross
>> segment/window boundaries.
>>
>> mikedunn
>>
>>>
>>> Thanks,
>>>
>>>
>>>
>>> On Wed, Jul 7, 2010 at 6:38 PM, Michael Dunn wrote:
>>>
>>>> Varun,
>>>>
>>>> On Wed, Jul 7, 2010 at 1:49 AM, varoonian . wrote:
>>>>
>>>>>
>>>>>
>>>>> Hello,
>>>>>
>>>>> I need to connect the TMS320"6416" DSK to the Virtex-5 FPGA.
>>>>>
>>>>> In order to do that I need to know the *IO functionalites of the DSK.
>>>>> *
>>>>>
>>>>
>>>> If you are interested in performance and flexibility, I suggest that you
>>>> configure your FPGA as a memory mapped device [all access is by reading and
>>>> writing memory locations]. You don't need to worry about any other 'I/O'
>>>> capabilities. If you can afford it, use a 32 bit data interface [as opposed
>>>> to 16 or 8 bits].
>>>>
>>>>
>>>>> **Can anyone kindly suggest any manuals or documents to go about
>>>>> before programming the EMIF on the DSK. Programming examples will be of
>>>>> great help to me.
>>>>>
>>>>
>>>> The only EMIF programming that you will need to do is a one time setup.
>>>> Review the EMIF setup in the DSK GEL file - you may be able to use them 'as
>>>> is' or you might have to change 1 value for your application.
>>>> Check spru190.pdf and look up the 'spru' number for the EMIF manual.
>>>>
>>>>>
>>>>> Do I also need to learn about GPIO ??
>>>>>
>>>>
>>>> no.
>>>>
>>>> mikedunn
>>>>
>>>>>
>>>>> Thanks,
>>>>>
>>>>> --
>>>>> Varun
>>>>>
>>>>>
>>>>
>>>>
>>>>
>>>> --
>>>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>>>>
>>>
>>>
>>>
>>> --
>>> Varun
>>> --
>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>> --
> Varun
>
--
Varun
Reply by ●July 22, 20102010-07-22
Varun,
On Wed, Jul 21, 2010 at 6:17 PM, varoonian . wrote:
> Dear Mr.Dunn,
>
> I read about the EMIF registers and the gel file which sets the memory map
> for the DSK6416.
>
> I activated the CE0 space for SDRAM by configuring the *MTYPE* field in
> the *CECTL0 register*. Is this correct ? After that initialized the SDRAM
> by turning *INIT* field in the* EMIFA_SDCTL register.*
>
Yes, but... you need to follow the steps below. Specifically, you need to
initialize all of the bits in the SDCTL register [like the GEL file does] as
your last EMIF setup write.
"The EMIF automatically clears the INIT field to zero after it performs
SDRAM
initialization. When RESET goes inactive, none of the CE spaces will be
configured
as SDRAM, so the INIT field will quickly change from 1 to 0. The CPU
should initialize all of the CE space control registers and the SDRAM
extension
register before it sets the INIT bit back to 1."
>
> Is there a way to set the CE1space for SDRAM or Daughter Card ? .. or is
> it reserved ?
>
I'm not sure that I understand the question, but I will try to explain 'CE
spaces'.
There is nothing special about 'CEn spaces', except for CE1 being enabled
for booting. The four CE spaces are simply a decode of the 4 MSBs of a 32
bit address.
CE0-1000b
CE1-1001b
CE2-1010b
CE3-1011b
If you make a custom board, you could put SDRAM in any, all, or none of the
CE spaces.
The designers of the 6713 DSK have hardwired CE0 to SDRAM and CE1 to flash
and on board control logic. CE2 and CE3 are hardwired to the daughtercard
connector.
mikedunn
>
> For the CSL implementation is it enough if you include the necessary CSL
> header file.. for example say I want to initialise the INIT bit in
> SDRAM_CTL..
>
> *#include*
> *#include*
>
> void main()
> {
>
> #define DC_REG 0x60000001
>
> #define EMIFA_GCTL 0x01800000
> #define EMIFA_CE1 0x01800004
> #define EMIFA_CE0 0x01800008
> #define EMIFA_CE2 0x01800010
> #define EMIFA_CE3 0x01800014
> #define EMIFA_SDRAMCTL 0x01800018
> /* other macros as well for the rest of the EMIFA register */
>
> *(int*)EMIFA_CE0 =0xFFFFFF33;
>
> *(int*)EMIFA_SDRAMEXT = 0x001faf4d;
>
> // setting INIT bit to 1 -- Initializing SDRAM //
>
> //*(int*)EMIFA_SDRAMCTL =0x47115000;
>
> /* CSL implemenation */
>
> *EMIFA_SDCTL_INIT_YES;*
>
> }
>
> Regards,
>
> Varun
>
> On Sat, Jul 10, 2010 at 2:38 PM, varoonian . wrote:
>
>> Thanks a lot Mr.Dunn. I'm looking into it.
>>
>> Regards,
>> On Thu, Jul 8, 2010 at 10:06 AM, Michael Dunn wrote:
>>
>>> Varun,
>>>
>>> On Thu, Jul 8, 2010 at 12:42 AM, varoonian . wrote:
>>>
>>>> Dear Mr.Dunn,
>>>>
>>>> Thank you very much.
>>>>
>>>> I will be using the DDR RAM ( 256 MB ) on the Virtex-5 Board since the
>>>> SDRAM of 16 MB on the DSK isn't sufficient.
>>>>
>>>
>>> You may want to use the 16 MB for code/data that requires more frequent
>>> access
>>> I am assuming that the Virtex-5 Board will be accessed by
>>> 6416_EMIF_async->DCIF_>Virtex_MemController->DDR_RAM.
>>> I anticipate that this will be a much slower access path.
>>>
>>>>
>>>> But I notice the EMIFA has only 22 address lines, which means I'll be
>>>> able to access only 2^22 = approx (4MB) of external memory. How does one
>>>> deal with this kind of problem ?
>>>>
>>>
>>> Actually the device EMIFA can access 2^22 64bit locations [refer to 'byte
>>> enables'].
>>> Some thoughts are:
>>>
>>> Divide the memory into 8 segments and use the existing DC interface
>>> signals [128MB].
>>> CE2 & !DB_CNTL0 & !DB_CNTL1 = MemSpace0 [16MB ea]
>>> CE2 & !DB_CNTL0 & DB_CNTL1 = MemSpace1
>>> CE2 & DB_CNTL0 & !DB_CNTL1 = MemSpace2
>>> CE2 & DB_CNTL0 & DB_CNTL1 = MemSpace3
>>> CE3 & !DB_CNTL0 & !DB_CNTL1 = MemSpace4
>>> CE3 & !DB_CNTL0 & DB_CNTL1 = MemSpace5
>>> CE3 & DB_CNTL0 & !DB_CNTL1 = MemSpace6
>>> CE3 & DB_CNTL0 & DB_CNTL1 = MemSpace7
>>>
>>> Always access 16MB memory 'windows' via CE2.
>>> Define a single register in CE3 space that defines the high order address
>>> bits [which effectively defines where the memory window is in the address
>>> space.
>>>
>>> !!NOTE!!:
>>> Any of these solutions will require some special handling in software.
>>> If your application is dealing with large data sets, keep the data
>>> separate from the code and ensure that each data set/buffer is contained
>>> within a single memory segment/window.
>>> Follow the same guidelines for your code by not letting it cross
>>> segment/window boundaries.
>>>
>>> mikedunn
>>>
>>>>
>>>> Thanks,
>>>>
>>>>
>>>>
>>>> On Wed, Jul 7, 2010 at 6:38 PM, Michael Dunn wrote:
>>>>
>>>>> Varun,
>>>>>
>>>>> On Wed, Jul 7, 2010 at 1:49 AM, varoonian . wrote:
>>>>>
>>>>>>
>>>>>>
>>>>>> Hello,
>>>>>>
>>>>>> I need to connect the TMS320"6416" DSK to the Virtex-5 FPGA.
>>>>>>
>>>>>> In order to do that I need to know the *IO functionalites of the
>>>>>> DSK. *
>>>>>>
>>>>>
>>>>> If you are interested in performance and flexibility, I suggest that
>>>>> you configure your FPGA as a memory mapped device [all access is by reading
>>>>> and writing memory locations]. You don't need to worry about any other 'I/O'
>>>>> capabilities. If you can afford it, use a 32 bit data interface [as opposed
>>>>> to 16 or 8 bits].
>>>>>
>>>>>
>>>>>> **Can anyone kindly suggest any manuals or documents to go about
>>>>>> before programming the EMIF on the DSK. Programming examples will be of
>>>>>> great help to me.
>>>>>>
>>>>>
>>>>> The only EMIF programming that you will need to do is a one time setup.
>>>>> Review the EMIF setup in the DSK GEL file - you may be able to use them 'as
>>>>> is' or you might have to change 1 value for your application.
>>>>> Check spru190.pdf and look up the 'spru' number for the EMIF manual.
>>>>>
>>>>>>
>>>>>> Do I also need to learn about GPIO ??
>>>>>>
>>>>>
>>>>> no.
>>>>>
>>>>> mikedunn
>>>>>
>>>>>>
>>>>>> Thanks,
>>>>>>
>>>>>> --
>>>>>> Varun
>>>>>>
>>>>>>
>>>>>
>>>>>
>>>>>
>>>>> --
>>>>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>>>>>
>>>>
>>>>
>>>>
>>>> --
>>>> Varun
>>>>
>>>
>>>
>>>
>>> --
>>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>>> --
>> Varun
>> --
> Varun
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
On Wed, Jul 21, 2010 at 6:17 PM, varoonian . wrote:
> Dear Mr.Dunn,
>
> I read about the EMIF registers and the gel file which sets the memory map
> for the DSK6416.
>
> I activated the CE0 space for SDRAM by configuring the *MTYPE* field in
> the *CECTL0 register*. Is this correct ? After that initialized the SDRAM
> by turning *INIT* field in the* EMIFA_SDCTL register.*
>
Yes, but... you need to follow the steps below. Specifically, you need to
initialize all of the bits in the SDCTL register [like the GEL file does] as
your last EMIF setup write.
"The EMIF automatically clears the INIT field to zero after it performs
SDRAM
initialization. When RESET goes inactive, none of the CE spaces will be
configured
as SDRAM, so the INIT field will quickly change from 1 to 0. The CPU
should initialize all of the CE space control registers and the SDRAM
extension
register before it sets the INIT bit back to 1."
>
> Is there a way to set the CE1space for SDRAM or Daughter Card ? .. or is
> it reserved ?
>
I'm not sure that I understand the question, but I will try to explain 'CE
spaces'.
There is nothing special about 'CEn spaces', except for CE1 being enabled
for booting. The four CE spaces are simply a decode of the 4 MSBs of a 32
bit address.
CE0-1000b
CE1-1001b
CE2-1010b
CE3-1011b
If you make a custom board, you could put SDRAM in any, all, or none of the
CE spaces.
The designers of the 6713 DSK have hardwired CE0 to SDRAM and CE1 to flash
and on board control logic. CE2 and CE3 are hardwired to the daughtercard
connector.
mikedunn
>
> For the CSL implementation is it enough if you include the necessary CSL
> header file.. for example say I want to initialise the INIT bit in
> SDRAM_CTL..
>
> *#include*
> *#include*
>
> void main()
> {
>
> #define DC_REG 0x60000001
>
> #define EMIFA_GCTL 0x01800000
> #define EMIFA_CE1 0x01800004
> #define EMIFA_CE0 0x01800008
> #define EMIFA_CE2 0x01800010
> #define EMIFA_CE3 0x01800014
> #define EMIFA_SDRAMCTL 0x01800018
> /* other macros as well for the rest of the EMIFA register */
>
> *(int*)EMIFA_CE0 =0xFFFFFF33;
>
> *(int*)EMIFA_SDRAMEXT = 0x001faf4d;
>
> // setting INIT bit to 1 -- Initializing SDRAM //
>
> //*(int*)EMIFA_SDRAMCTL =0x47115000;
>
> /* CSL implemenation */
>
> *EMIFA_SDCTL_INIT_YES;*
>
> }
>
> Regards,
>
> Varun
>
> On Sat, Jul 10, 2010 at 2:38 PM, varoonian . wrote:
>
>> Thanks a lot Mr.Dunn. I'm looking into it.
>>
>> Regards,
>> On Thu, Jul 8, 2010 at 10:06 AM, Michael Dunn wrote:
>>
>>> Varun,
>>>
>>> On Thu, Jul 8, 2010 at 12:42 AM, varoonian . wrote:
>>>
>>>> Dear Mr.Dunn,
>>>>
>>>> Thank you very much.
>>>>
>>>> I will be using the DDR RAM ( 256 MB ) on the Virtex-5 Board since the
>>>> SDRAM of 16 MB on the DSK isn't sufficient.
>>>>
>>>
>>> You may want to use the 16 MB for code/data that requires more frequent
>>> access
>>> I am assuming that the Virtex-5 Board will be accessed by
>>> 6416_EMIF_async->DCIF_>Virtex_MemController->DDR_RAM.
>>> I anticipate that this will be a much slower access path.
>>>
>>>>
>>>> But I notice the EMIFA has only 22 address lines, which means I'll be
>>>> able to access only 2^22 = approx (4MB) of external memory. How does one
>>>> deal with this kind of problem ?
>>>>
>>>
>>> Actually the device EMIFA can access 2^22 64bit locations [refer to 'byte
>>> enables'].
>>> Some thoughts are:
>>>
>>> Divide the memory into 8 segments and use the existing DC interface
>>> signals [128MB].
>>> CE2 & !DB_CNTL0 & !DB_CNTL1 = MemSpace0 [16MB ea]
>>> CE2 & !DB_CNTL0 & DB_CNTL1 = MemSpace1
>>> CE2 & DB_CNTL0 & !DB_CNTL1 = MemSpace2
>>> CE2 & DB_CNTL0 & DB_CNTL1 = MemSpace3
>>> CE3 & !DB_CNTL0 & !DB_CNTL1 = MemSpace4
>>> CE3 & !DB_CNTL0 & DB_CNTL1 = MemSpace5
>>> CE3 & DB_CNTL0 & !DB_CNTL1 = MemSpace6
>>> CE3 & DB_CNTL0 & DB_CNTL1 = MemSpace7
>>>
>>> Always access 16MB memory 'windows' via CE2.
>>> Define a single register in CE3 space that defines the high order address
>>> bits [which effectively defines where the memory window is in the address
>>> space.
>>>
>>> !!NOTE!!:
>>> Any of these solutions will require some special handling in software.
>>> If your application is dealing with large data sets, keep the data
>>> separate from the code and ensure that each data set/buffer is contained
>>> within a single memory segment/window.
>>> Follow the same guidelines for your code by not letting it cross
>>> segment/window boundaries.
>>>
>>> mikedunn
>>>
>>>>
>>>> Thanks,
>>>>
>>>>
>>>>
>>>> On Wed, Jul 7, 2010 at 6:38 PM, Michael Dunn wrote:
>>>>
>>>>> Varun,
>>>>>
>>>>> On Wed, Jul 7, 2010 at 1:49 AM, varoonian . wrote:
>>>>>
>>>>>>
>>>>>>
>>>>>> Hello,
>>>>>>
>>>>>> I need to connect the TMS320"6416" DSK to the Virtex-5 FPGA.
>>>>>>
>>>>>> In order to do that I need to know the *IO functionalites of the
>>>>>> DSK. *
>>>>>>
>>>>>
>>>>> If you are interested in performance and flexibility, I suggest that
>>>>> you configure your FPGA as a memory mapped device [all access is by reading
>>>>> and writing memory locations]. You don't need to worry about any other 'I/O'
>>>>> capabilities. If you can afford it, use a 32 bit data interface [as opposed
>>>>> to 16 or 8 bits].
>>>>>
>>>>>
>>>>>> **Can anyone kindly suggest any manuals or documents to go about
>>>>>> before programming the EMIF on the DSK. Programming examples will be of
>>>>>> great help to me.
>>>>>>
>>>>>
>>>>> The only EMIF programming that you will need to do is a one time setup.
>>>>> Review the EMIF setup in the DSK GEL file - you may be able to use them 'as
>>>>> is' or you might have to change 1 value for your application.
>>>>> Check spru190.pdf and look up the 'spru' number for the EMIF manual.
>>>>>
>>>>>>
>>>>>> Do I also need to learn about GPIO ??
>>>>>>
>>>>>
>>>>> no.
>>>>>
>>>>> mikedunn
>>>>>
>>>>>>
>>>>>> Thanks,
>>>>>>
>>>>>> --
>>>>>> Varun
>>>>>>
>>>>>>
>>>>>
>>>>>
>>>>>
>>>>> --
>>>>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>>>>>
>>>>
>>>>
>>>>
>>>> --
>>>> Varun
>>>>
>>>
>>>
>>>
>>> --
>>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>>> --
>> Varun
>> --
> Varun
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
Reply by ●July 23, 20102010-07-23
Varun,
Please respond to the group. This is for everyone to have a chance to learn
from the discussion of ideas.
On Fri, Jul 23, 2010 at 2:17 AM, varoonian . wrote:
> Dear Mr.Dunn,
>
> Yes. I noticed that the INIT bit goes back to '0' once the initialization
> is complete in the DSK 6416. I took care to set the '*MTYPE' * in the
> CECTL0 register as a 32-bit SDRAM before setting *INIT bit to 1.* I
> checked the data present in the CE0 space in CCS by viewing the memory
> content at CE0 and plotted the data just to verify.
>
> In your previous email you had mentioned about diving the memory into 8
> segments.
>
> "Divide the memory into 8 segments and use the existing DC interface
> signals [128MB].
> CE2 & !DB_CNTL0 & !DB_CNTL1 = MemSpace0 [16MB ea]
> CE2 & !DB_CNTL0 & DB_CNTL1 = MemSpace1
> ..............................
> ..............................
>
> CE3 & DB_CNTL0 & !DB_CNTL1 = MemSpace6
> CE3 & DB_CNTL0 & DB_CNTL1 = MemSpace7" .. * Did you mean DC_CNTL ?
> What happens when DC_CNTL0=0 and DC_CNTL_1=0 ? I do not understand that
> part.*
>
Yes, I meant DC_CNTL.
Let me explain it this way -
DC furnishes A2:A21
DC_CNTL0 = A22
DC_CNTL1 = A23
CE34 low [and board_enable]
CE34 high [and board_enable]
If you need more address space, you can use
DC furnishes A2:A21, memory access is always done using CE3.
CE4 writes to a latch were each bit represents A22, A23, A24, A25, A26, A27.
You would do this write to select a particular segment/bank of memory before
accessing.
mikedunn
> *
> *
> *Thanks,*
> On Wed, Jul 21, 2010 at 11:01 PM, Michael Dunn wrote:
>
>> Varun,
>>
>> On Wed, Jul 21, 2010 at 6:17 PM, varoonian . wrote:
>>
>>> Dear Mr.Dunn,
>>>
>>> I read about the EMIF registers and the gel file which sets the memory
>>> map for the DSK6416.
>>>
>>> I activated the CE0 space for SDRAM by configuring the *MTYPE* field in
>>> the *CECTL0 register*. Is this correct ? After that initialized the
>>> SDRAM by turning *INIT* field in the* EMIFA_SDCTL register.*
>>>
>>
>> Yes, but... you need to follow the steps below. Specifically, you need to
>> initialize all of the bits in the SDCTL register [like the GEL file does] as
>> your last EMIF setup write.
>>
>> "The EMIF automatically clears the INIT field to zero after it performs
>> SDRAM
>> initialization. When RESET goes inactive, none of the CE spaces will be
>> configured
>> as SDRAM, so the INIT field will quickly change from 1 to 0. The CPU
>> should initialize all of the CE space control registers and the SDRAM
>> extension
>> register before it sets the INIT bit back to 1."
>>
>>>
>>> Is there a way to set the CE1space for SDRAM or Daughter Card ? .. or is
>>> it reserved ?
>>>
>>
>> I'm not sure that I understand the question, but I will try to explain 'CE
>> spaces'.
>> There is nothing special about 'CEn spaces', except for CE1 being enabled
>> for booting. The four CE spaces are simply a decode of the 4 MSBs of a 32
>> bit address.
>> CE0-1000b
>> CE1-1001b
>> CE2-1010b
>> CE3-1011b
>> If you make a custom board, you could put SDRAM in any, all, or none of
>> the CE spaces.
>> The designers of the 6713 DSK have hardwired CE0 to SDRAM and CE1 to flash
>> and on board control logic. CE2 and CE3 are hardwired to the daughtercard
>> connector.
>>
>> mikedunn
>>
>>>
>>> For the CSL implementation is it enough if you include the necessary CSL
>>> header file.. for example say I want to initialise the INIT bit in
>>> SDRAM_CTL..
>>>
>>> *#include*
>>> *#include*
>>>
>>> void main()
>>> {
>>>
>>> #define DC_REG 0x60000001
>>>
>>> #define EMIFA_GCTL 0x01800000
>>> #define EMIFA_CE1 0x01800004
>>> #define EMIFA_CE0 0x01800008
>>> #define EMIFA_CE2 0x01800010
>>> #define EMIFA_CE3 0x01800014
>>> #define EMIFA_SDRAMCTL 0x01800018
>>> /* other macros as well for the rest of the EMIFA register */
>>>
>>> *(int*)EMIFA_CE0 =0xFFFFFF33;
>>>
>>> *(int*)EMIFA_SDRAMEXT = 0x001faf4d;
>>>
>>> // setting INIT bit to 1 -- Initializing SDRAM //
>>>
>>> //*(int*)EMIFA_SDRAMCTL =0x47115000;
>>>
>>> /* CSL implemenation */
>>>
>>> *EMIFA_SDCTL_INIT_YES;*
>>>
>>> }
>>>
>>> Regards,
>>>
>>> Varun
>>>
>>>
>>>
>>> On Sat, Jul 10, 2010 at 2:38 PM, varoonian . wrote:
>>>
>>>> Thanks a lot Mr.Dunn. I'm looking into it.
>>>>
>>>> Regards,
>>>>
>>>>
>>>> On Thu, Jul 8, 2010 at 10:06 AM, Michael Dunn wrote:
>>>>
>>>>> Varun,
>>>>>
>>>>> On Thu, Jul 8, 2010 at 12:42 AM, varoonian . wrote:
>>>>>
>>>>>> Dear Mr.Dunn,
>>>>>>
>>>>>> Thank you very much.
>>>>>>
>>>>>> I will be using the DDR RAM ( 256 MB ) on the Virtex-5 Board since the
>>>>>> SDRAM of 16 MB on the DSK isn't sufficient.
>>>>>>
>>>>>
>>>>> You may want to use the 16 MB for code/data that requires more frequent
>>>>> access
>>>>> I am assuming that the Virtex-5 Board will be accessed by
>>>>> 6416_EMIF_async->DCIF_>Virtex_MemController->DDR_RAM.
>>>>> I anticipate that this will be a much slower access path.
>>>>>
>>>>>>
>>>>>> But I notice the EMIFA has only 22 address lines, which means I'll be
>>>>>> able to access only 2^22 = approx (4MB) of external memory. How does one
>>>>>> deal with this kind of problem ?
>>>>>>
>>>>>
>>>>> Actually the device EMIFA can access 2^22 64bit locations [refer to
>>>>> 'byte enables'].
>>>>> Some thoughts are:
>>>>>
>>>>> Divide the memory into 8 segments and use the existing DC interface
>>>>> signals [128MB].
>>>>> CE2 & !DB_CNTL0 & !DB_CNTL1 = MemSpace0 [16MB ea]
>>>>> CE2 & !DB_CNTL0 & DB_CNTL1 = MemSpace1
>>>>> CE2 & DB_CNTL0 & !DB_CNTL1 = MemSpace2
>>>>> CE2 & DB_CNTL0 & DB_CNTL1 = MemSpace3
>>>>> CE3 & !DB_CNTL0 & !DB_CNTL1 = MemSpace4
>>>>> CE3 & !DB_CNTL0 & DB_CNTL1 = MemSpace5
>>>>> CE3 & DB_CNTL0 & !DB_CNTL1 = MemSpace6
>>>>> CE3 & DB_CNTL0 & DB_CNTL1 = MemSpace7
>>>>>
>>>>> Always access 16MB memory 'windows' via CE2.
>>>>> Define a single register in CE3 space that defines the high order
>>>>> address bits [which effectively defines where the memory window is in the
>>>>> address space.
>>>>>
>>>>> !!NOTE!!:
>>>>> Any of these solutions will require some special handling in software.
>>>>> If your application is dealing with large data sets, keep the data
>>>>> separate from the code and ensure that each data set/buffer is contained
>>>>> within a single memory segment/window.
>>>>> Follow the same guidelines for your code by not letting it cross
>>>>> segment/window boundaries.
>>>>>
>>>>> mikedunn
>>>>>
>>>>>>
>>>>>> Thanks,
>>>>>>
>>>>>>
>>>>>>
>>>>>> On Wed, Jul 7, 2010 at 6:38 PM, Michael Dunn >>>>>> > wrote:
>>>>>>
>>>>>>> Varun,
>>>>>>>
>>>>>>> On Wed, Jul 7, 2010 at 1:49 AM, varoonian . wrote:
>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> Hello,
>>>>>>>>
>>>>>>>> I need to connect the TMS320"6416" DSK to the Virtex-5 FPGA.
>>>>>>>>
>>>>>>>> In order to do that I need to know the *IO functionalites of the
>>>>>>>> DSK. *
>>>>>>>>
>>>>>>>
>>>>>>> If you are interested in performance and flexibility, I suggest that
>>>>>>> you configure your FPGA as a memory mapped device [all access is by reading
>>>>>>> and writing memory locations]. You don't need to worry about any other 'I/O'
>>>>>>> capabilities. If you can afford it, use a 32 bit data interface [as opposed
>>>>>>> to 16 or 8 bits].
>>>>>>>
>>>>>>>
>>>>>>>> **Can anyone kindly suggest any manuals or documents to go about
>>>>>>>> before programming the EMIF on the DSK. Programming examples will be of
>>>>>>>> great help to me.
>>>>>>>>
>>>>>>>
>>>>>>> The only EMIF programming that you will need to do is a one time
>>>>>>> setup. Review the EMIF setup in the DSK GEL file - you may be able to use
>>>>>>> them 'as is' or you might have to change 1 value for your application.
>>>>>>> Check spru190.pdf and look up the 'spru' number for the EMIF manual.
>>>>>>>
>>>>>>>>
>>>>>>>> Do I also need to learn about GPIO ??
>>>>>>>>
>>>>>>>
>>>>>>> no.
>>>>>>>
>>>>>>> mikedunn
>>>>>>>
>>>>>>>>
>>>>>>>> Thanks,
>>>>>>>>
>>>>>>>> --
>>>>>>>> Varun
>>>>>>>>
>>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> --
>>>>>>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>> --
>>>>>> Varun
>>>>>>
>>>>>
>>>>>
>>>>>
>>>>> --
>>>>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>>>>>
>>>>
>>>>
>>>>
>>>> --
>>>> Varun
>>>>
>>>
>>>
>>>
>>> --
>>> Varun
>>> --
>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>> --
> Varun
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
Please respond to the group. This is for everyone to have a chance to learn
from the discussion of ideas.
On Fri, Jul 23, 2010 at 2:17 AM, varoonian . wrote:
> Dear Mr.Dunn,
>
> Yes. I noticed that the INIT bit goes back to '0' once the initialization
> is complete in the DSK 6416. I took care to set the '*MTYPE' * in the
> CECTL0 register as a 32-bit SDRAM before setting *INIT bit to 1.* I
> checked the data present in the CE0 space in CCS by viewing the memory
> content at CE0 and plotted the data just to verify.
>
> In your previous email you had mentioned about diving the memory into 8
> segments.
>
> "Divide the memory into 8 segments and use the existing DC interface
> signals [128MB].
> CE2 & !DB_CNTL0 & !DB_CNTL1 = MemSpace0 [16MB ea]
> CE2 & !DB_CNTL0 & DB_CNTL1 = MemSpace1
> ..............................
> ..............................
>
> CE3 & DB_CNTL0 & !DB_CNTL1 = MemSpace6
> CE3 & DB_CNTL0 & DB_CNTL1 = MemSpace7" .. * Did you mean DC_CNTL ?
> What happens when DC_CNTL0=0 and DC_CNTL_1=0 ? I do not understand that
> part.*
>
Yes, I meant DC_CNTL.
Let me explain it this way -
DC furnishes A2:A21
DC_CNTL0 = A22
DC_CNTL1 = A23
CE34 low [and board_enable]
CE34 high [and board_enable]
If you need more address space, you can use
DC furnishes A2:A21, memory access is always done using CE3.
CE4 writes to a latch were each bit represents A22, A23, A24, A25, A26, A27.
You would do this write to select a particular segment/bank of memory before
accessing.
mikedunn
> *
> *
> *Thanks,*
> On Wed, Jul 21, 2010 at 11:01 PM, Michael Dunn wrote:
>
>> Varun,
>>
>> On Wed, Jul 21, 2010 at 6:17 PM, varoonian . wrote:
>>
>>> Dear Mr.Dunn,
>>>
>>> I read about the EMIF registers and the gel file which sets the memory
>>> map for the DSK6416.
>>>
>>> I activated the CE0 space for SDRAM by configuring the *MTYPE* field in
>>> the *CECTL0 register*. Is this correct ? After that initialized the
>>> SDRAM by turning *INIT* field in the* EMIFA_SDCTL register.*
>>>
>>
>> Yes, but... you need to follow the steps below. Specifically, you need to
>> initialize all of the bits in the SDCTL register [like the GEL file does] as
>> your last EMIF setup write.
>>
>> "The EMIF automatically clears the INIT field to zero after it performs
>> SDRAM
>> initialization. When RESET goes inactive, none of the CE spaces will be
>> configured
>> as SDRAM, so the INIT field will quickly change from 1 to 0. The CPU
>> should initialize all of the CE space control registers and the SDRAM
>> extension
>> register before it sets the INIT bit back to 1."
>>
>>>
>>> Is there a way to set the CE1space for SDRAM or Daughter Card ? .. or is
>>> it reserved ?
>>>
>>
>> I'm not sure that I understand the question, but I will try to explain 'CE
>> spaces'.
>> There is nothing special about 'CEn spaces', except for CE1 being enabled
>> for booting. The four CE spaces are simply a decode of the 4 MSBs of a 32
>> bit address.
>> CE0-1000b
>> CE1-1001b
>> CE2-1010b
>> CE3-1011b
>> If you make a custom board, you could put SDRAM in any, all, or none of
>> the CE spaces.
>> The designers of the 6713 DSK have hardwired CE0 to SDRAM and CE1 to flash
>> and on board control logic. CE2 and CE3 are hardwired to the daughtercard
>> connector.
>>
>> mikedunn
>>
>>>
>>> For the CSL implementation is it enough if you include the necessary CSL
>>> header file.. for example say I want to initialise the INIT bit in
>>> SDRAM_CTL..
>>>
>>> *#include*
>>> *#include*
>>>
>>> void main()
>>> {
>>>
>>> #define DC_REG 0x60000001
>>>
>>> #define EMIFA_GCTL 0x01800000
>>> #define EMIFA_CE1 0x01800004
>>> #define EMIFA_CE0 0x01800008
>>> #define EMIFA_CE2 0x01800010
>>> #define EMIFA_CE3 0x01800014
>>> #define EMIFA_SDRAMCTL 0x01800018
>>> /* other macros as well for the rest of the EMIFA register */
>>>
>>> *(int*)EMIFA_CE0 =0xFFFFFF33;
>>>
>>> *(int*)EMIFA_SDRAMEXT = 0x001faf4d;
>>>
>>> // setting INIT bit to 1 -- Initializing SDRAM //
>>>
>>> //*(int*)EMIFA_SDRAMCTL =0x47115000;
>>>
>>> /* CSL implemenation */
>>>
>>> *EMIFA_SDCTL_INIT_YES;*
>>>
>>> }
>>>
>>> Regards,
>>>
>>> Varun
>>>
>>>
>>>
>>> On Sat, Jul 10, 2010 at 2:38 PM, varoonian . wrote:
>>>
>>>> Thanks a lot Mr.Dunn. I'm looking into it.
>>>>
>>>> Regards,
>>>>
>>>>
>>>> On Thu, Jul 8, 2010 at 10:06 AM, Michael Dunn wrote:
>>>>
>>>>> Varun,
>>>>>
>>>>> On Thu, Jul 8, 2010 at 12:42 AM, varoonian . wrote:
>>>>>
>>>>>> Dear Mr.Dunn,
>>>>>>
>>>>>> Thank you very much.
>>>>>>
>>>>>> I will be using the DDR RAM ( 256 MB ) on the Virtex-5 Board since the
>>>>>> SDRAM of 16 MB on the DSK isn't sufficient.
>>>>>>
>>>>>
>>>>> You may want to use the 16 MB for code/data that requires more frequent
>>>>> access
>>>>> I am assuming that the Virtex-5 Board will be accessed by
>>>>> 6416_EMIF_async->DCIF_>Virtex_MemController->DDR_RAM.
>>>>> I anticipate that this will be a much slower access path.
>>>>>
>>>>>>
>>>>>> But I notice the EMIFA has only 22 address lines, which means I'll be
>>>>>> able to access only 2^22 = approx (4MB) of external memory. How does one
>>>>>> deal with this kind of problem ?
>>>>>>
>>>>>
>>>>> Actually the device EMIFA can access 2^22 64bit locations [refer to
>>>>> 'byte enables'].
>>>>> Some thoughts are:
>>>>>
>>>>> Divide the memory into 8 segments and use the existing DC interface
>>>>> signals [128MB].
>>>>> CE2 & !DB_CNTL0 & !DB_CNTL1 = MemSpace0 [16MB ea]
>>>>> CE2 & !DB_CNTL0 & DB_CNTL1 = MemSpace1
>>>>> CE2 & DB_CNTL0 & !DB_CNTL1 = MemSpace2
>>>>> CE2 & DB_CNTL0 & DB_CNTL1 = MemSpace3
>>>>> CE3 & !DB_CNTL0 & !DB_CNTL1 = MemSpace4
>>>>> CE3 & !DB_CNTL0 & DB_CNTL1 = MemSpace5
>>>>> CE3 & DB_CNTL0 & !DB_CNTL1 = MemSpace6
>>>>> CE3 & DB_CNTL0 & DB_CNTL1 = MemSpace7
>>>>>
>>>>> Always access 16MB memory 'windows' via CE2.
>>>>> Define a single register in CE3 space that defines the high order
>>>>> address bits [which effectively defines where the memory window is in the
>>>>> address space.
>>>>>
>>>>> !!NOTE!!:
>>>>> Any of these solutions will require some special handling in software.
>>>>> If your application is dealing with large data sets, keep the data
>>>>> separate from the code and ensure that each data set/buffer is contained
>>>>> within a single memory segment/window.
>>>>> Follow the same guidelines for your code by not letting it cross
>>>>> segment/window boundaries.
>>>>>
>>>>> mikedunn
>>>>>
>>>>>>
>>>>>> Thanks,
>>>>>>
>>>>>>
>>>>>>
>>>>>> On Wed, Jul 7, 2010 at 6:38 PM, Michael Dunn >>>>>> > wrote:
>>>>>>
>>>>>>> Varun,
>>>>>>>
>>>>>>> On Wed, Jul 7, 2010 at 1:49 AM, varoonian . wrote:
>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> Hello,
>>>>>>>>
>>>>>>>> I need to connect the TMS320"6416" DSK to the Virtex-5 FPGA.
>>>>>>>>
>>>>>>>> In order to do that I need to know the *IO functionalites of the
>>>>>>>> DSK. *
>>>>>>>>
>>>>>>>
>>>>>>> If you are interested in performance and flexibility, I suggest that
>>>>>>> you configure your FPGA as a memory mapped device [all access is by reading
>>>>>>> and writing memory locations]. You don't need to worry about any other 'I/O'
>>>>>>> capabilities. If you can afford it, use a 32 bit data interface [as opposed
>>>>>>> to 16 or 8 bits].
>>>>>>>
>>>>>>>
>>>>>>>> **Can anyone kindly suggest any manuals or documents to go about
>>>>>>>> before programming the EMIF on the DSK. Programming examples will be of
>>>>>>>> great help to me.
>>>>>>>>
>>>>>>>
>>>>>>> The only EMIF programming that you will need to do is a one time
>>>>>>> setup. Review the EMIF setup in the DSK GEL file - you may be able to use
>>>>>>> them 'as is' or you might have to change 1 value for your application.
>>>>>>> Check spru190.pdf and look up the 'spru' number for the EMIF manual.
>>>>>>>
>>>>>>>>
>>>>>>>> Do I also need to learn about GPIO ??
>>>>>>>>
>>>>>>>
>>>>>>> no.
>>>>>>>
>>>>>>> mikedunn
>>>>>>>
>>>>>>>>
>>>>>>>> Thanks,
>>>>>>>>
>>>>>>>> --
>>>>>>>> Varun
>>>>>>>>
>>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> --
>>>>>>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>> --
>>>>>> Varun
>>>>>>
>>>>>
>>>>>
>>>>>
>>>>> --
>>>>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>>>>>
>>>>
>>>>
>>>>
>>>> --
>>>> Varun
>>>>
>>>
>>>
>>>
>>> --
>>> Varun
>>> --
>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>> --
> Varun
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
Reply by ●July 23, 20102010-07-23
Oh I'm sorry I did not notice that in a hurry. Sorry about that.
On Fri, Jul 23, 2010 at 9:06 AM, Michael Dunn wrote:
> Varun,
>
> Please respond to the group. This is for everyone to have a chance to learn
> from the discussion of ideas.
>
> On Fri, Jul 23, 2010 at 2:17 AM, varoonian . wrote:
>
>> Dear Mr.Dunn,
>>
>> Yes. I noticed that the INIT bit goes back to '0' once the initialization
>> is complete in the DSK 6416. I took care to set the '*MTYPE' * in the
>> CECTL0 register as a 32-bit SDRAM before setting *INIT bit to 1.* I
>> checked the data present in the CE0 space in CCS by viewing the memory
>> content at CE0 and plotted the data just to verify.
>>
>> In your previous email you had mentioned about diving the memory into 8
>> segments.
>>
>> "Divide the memory into 8 segments and use the existing DC interface
>> signals [128MB].
>> CE2 & !DB_CNTL0 & !DB_CNTL1 = MemSpace0 [16MB ea]
>> CE2 & !DB_CNTL0 & DB_CNTL1 = MemSpace1
>> ..............................
>> ..............................
>>
>> CE3 & DB_CNTL0 & !DB_CNTL1 = MemSpace6
>> CE3 & DB_CNTL0 & DB_CNTL1 = MemSpace7" .. * Did you mean DC_CNTL ?
>> What happens when DC_CNTL0=0 and DC_CNTL_1=0 ? I do not understand that
>> part.*
>>
>
> Yes, I meant DC_CNTL.
>
> Let me explain it this way -
>
> DC furnishes A2:A21
> DC_CNTL0 = A22
> DC_CNTL1 = A23
> CE34 low [and board_enable]
> CE34 high [and board_enable]
>
> If you need more address space, you can use
>
> DC furnishes A2:A21, memory access is always done using CE3.
> CE4 writes to a latch were each bit represents A22, A23, A24, A25, A26,
> A27. You would do this write to select a particular segment/bank of memory
> before accessing.
>
> mikedunn
>> *
>> *
>> *Thanks,*
>> On Wed, Jul 21, 2010 at 11:01 PM, Michael Dunn wrote:
>>
>>> Varun,
>>>
>>> On Wed, Jul 21, 2010 at 6:17 PM, varoonian . wrote:
>>>
>>>> Dear Mr.Dunn,
>>>>
>>>> I read about the EMIF registers and the gel file which sets the memory
>>>> map for the DSK6416.
>>>>
>>>> I activated the CE0 space for SDRAM by configuring the *MTYPE* field in
>>>> the *CECTL0 register*. Is this correct ? After that initialized the
>>>> SDRAM by turning *INIT* field in the* EMIFA_SDCTL register.*
>>>>
>>>
>>> Yes, but... you need to follow the steps below. Specifically, you need to
>>> initialize all of the bits in the SDCTL register [like the GEL file does] as
>>> your last EMIF setup write.
>>>
>>> "The EMIF automatically clears the INIT field to zero after it performs
>>> SDRAM
>>> initialization. When RESET goes inactive, none of the CE spaces will be
>>> configured
>>> as SDRAM, so the INIT field will quickly change from 1 to 0. The CPU
>>> should initialize all of the CE space control registers and the SDRAM
>>> extension
>>> register before it sets the INIT bit back to 1."
>>>
>>>>
>>>> Is there a way to set the CE1space for SDRAM or Daughter Card ? .. or
>>>> is it reserved ?
>>>>
>>>
>>> I'm not sure that I understand the question, but I will try to explain
>>> 'CE spaces'.
>>> There is nothing special about 'CEn spaces', except for CE1 being enabled
>>> for booting. The four CE spaces are simply a decode of the 4 MSBs of a 32
>>> bit address.
>>> CE0-1000b
>>> CE1-1001b
>>> CE2-1010b
>>> CE3-1011b
>>> If you make a custom board, you could put SDRAM in any, all, or none of
>>> the CE spaces.
>>> The designers of the 6713 DSK have hardwired CE0 to SDRAM and CE1 to
>>> flash and on board control logic. CE2 and CE3 are hardwired to the
>>> daughtercard connector.
>>>
>>> mikedunn
>>>
>>>>
>>>> For the CSL implementation is it enough if you include the necessary CSL
>>>> header file.. for example say I want to initialise the INIT bit in
>>>> SDRAM_CTL..
>>>>
>>>> *#include*
>>>> *#include*
>>>>
>>>> void main()
>>>> {
>>>>
>>>> #define DC_REG 0x60000001
>>>>
>>>> #define EMIFA_GCTL 0x01800000
>>>> #define EMIFA_CE1 0x01800004
>>>> #define EMIFA_CE0 0x01800008
>>>> #define EMIFA_CE2 0x01800010
>>>> #define EMIFA_CE3 0x01800014
>>>> #define EMIFA_SDRAMCTL 0x01800018
>>>> /* other macros as well for the rest of the EMIFA register */
>>>>
>>>> *(int*)EMIFA_CE0 =0xFFFFFF33;
>>>>
>>>> *(int*)EMIFA_SDRAMEXT = 0x001faf4d;
>>>>
>>>> // setting INIT bit to 1 -- Initializing SDRAM //
>>>>
>>>> //*(int*)EMIFA_SDRAMCTL =0x47115000;
>>>>
>>>> /* CSL implemenation */
>>>>
>>>> *EMIFA_SDCTL_INIT_YES;*
>>>>
>>>> }
>>>>
>>>> Regards,
>>>>
>>>> Varun
>>>>
>>>>
>>>>
>>>> On Sat, Jul 10, 2010 at 2:38 PM, varoonian . wrote:
>>>>
>>>>> Thanks a lot Mr.Dunn. I'm looking into it.
>>>>>
>>>>> Regards,
>>>>>
>>>>>
>>>>> On Thu, Jul 8, 2010 at 10:06 AM, Michael Dunn >>>>> > wrote:
>>>>>
>>>>>> Varun,
>>>>>>
>>>>>> On Thu, Jul 8, 2010 at 12:42 AM, varoonian . wrote:
>>>>>>
>>>>>>> Dear Mr.Dunn,
>>>>>>>
>>>>>>> Thank you very much.
>>>>>>>
>>>>>>> I will be using the DDR RAM ( 256 MB ) on the Virtex-5 Board since
>>>>>>> the SDRAM of 16 MB on the DSK isn't sufficient.
>>>>>>>
>>>>>>
>>>>>> You may want to use the 16 MB for code/data that requires more
>>>>>> frequent access
>>>>>> I am assuming that the Virtex-5 Board will be accessed by
>>>>>> 6416_EMIF_async->DCIF_>Virtex_MemController->DDR_RAM.
>>>>>> I anticipate that this will be a much slower access path.
>>>>>>
>>>>>>>
>>>>>>> But I notice the EMIFA has only 22 address lines, which means I'll be
>>>>>>> able to access only 2^22 = approx (4MB) of external memory. How does one
>>>>>>> deal with this kind of problem ?
>>>>>>>
>>>>>>
>>>>>> Actually the device EMIFA can access 2^22 64bit locations [refer to
>>>>>> 'byte enables'].
>>>>>> Some thoughts are:
>>>>>>
>>>>>> Divide the memory into 8 segments and use the existing DC interface
>>>>>> signals [128MB].
>>>>>> CE2 & !DB_CNTL0 & !DB_CNTL1 = MemSpace0 [16MB ea]
>>>>>> CE2 & !DB_CNTL0 & DB_CNTL1 = MemSpace1
>>>>>> CE2 & DB_CNTL0 & !DB_CNTL1 = MemSpace2
>>>>>> CE2 & DB_CNTL0 & DB_CNTL1 = MemSpace3
>>>>>> CE3 & !DB_CNTL0 & !DB_CNTL1 = MemSpace4
>>>>>> CE3 & !DB_CNTL0 & DB_CNTL1 = MemSpace5
>>>>>> CE3 & DB_CNTL0 & !DB_CNTL1 = MemSpace6
>>>>>> CE3 & DB_CNTL0 & DB_CNTL1 = MemSpace7
>>>>>>
>>>>>> Always access 16MB memory 'windows' via CE2.
>>>>>> Define a single register in CE3 space that defines the high order
>>>>>> address bits [which effectively defines where the memory window is in the
>>>>>> address space.
>>>>>>
>>>>>> !!NOTE!!:
>>>>>> Any of these solutions will require some special handling in software.
>>>>>> If your application is dealing with large data sets, keep the data
>>>>>> separate from the code and ensure that each data set/buffer is contained
>>>>>> within a single memory segment/window.
>>>>>> Follow the same guidelines for your code by not letting it cross
>>>>>> segment/window boundaries.
>>>>>>
>>>>>> mikedunn
>>>>>>
>>>>>>>
>>>>>>> Thanks,
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> On Wed, Jul 7, 2010 at 6:38 PM, Michael Dunn <
>>>>>>> m...@gmail.com> wrote:
>>>>>>>
>>>>>>>> Varun,
>>>>>>>>
>>>>>>>> On Wed, Jul 7, 2010 at 1:49 AM, varoonian . wrote:
>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Hello,
>>>>>>>>>
>>>>>>>>> I need to connect the TMS320"6416" DSK to the Virtex-5 FPGA.
>>>>>>>>>
>>>>>>>>> In order to do that I need to know the *IO functionalites of the
>>>>>>>>> DSK. *
>>>>>>>>>
>>>>>>>>
>>>>>>>> If you are interested in performance and flexibility, I suggest that
>>>>>>>> you configure your FPGA as a memory mapped device [all access is by reading
>>>>>>>> and writing memory locations]. You don't need to worry about any other 'I/O'
>>>>>>>> capabilities. If you can afford it, use a 32 bit data interface [as opposed
>>>>>>>> to 16 or 8 bits].
>>>>>>>>
>>>>>>>>
>>>>>>>>> **Can anyone kindly suggest any manuals or documents to go about
>>>>>>>>> before programming the EMIF on the DSK. Programming examples will be of
>>>>>>>>> great help to me.
>>>>>>>>>
>>>>>>>>
>>>>>>>> The only EMIF programming that you will need to do is a one time
>>>>>>>> setup. Review the EMIF setup in the DSK GEL file - you may be able to use
>>>>>>>> them 'as is' or you might have to change 1 value for your application.
>>>>>>>> Check spru190.pdf and look up the 'spru' number for the EMIF manual.
>>>>>>>>
>>>>>>>>>
>>>>>>>>> Do I also need to learn about GPIO ??
>>>>>>>>>
>>>>>>>>
>>>>>>>> no.
>>>>>>>>
>>>>>>>> mikedunn
>>>>>>>>
>>>>>>>>>
>>>>>>>>> Thanks,
>>>>>>>>>
>>>>>>>>> --
>>>>>>>>> Varun
>>>>>>>>>
>>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> --
>>>>>>>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> --
>>>>>>> Varun
>>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>> --
>>>>>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>>>>>>
>>>>>
>>>>>
>>>>>
>>>>> --
>>>>> Varun
>>>>>
>>>>
>>>>
>>>>
>>>> --
>>>> Varun
>>>>
>>>
>>>
>>>
>>> --
>>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>>> --
>> Varun
>> --
> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>
--
Varun
On Fri, Jul 23, 2010 at 9:06 AM, Michael Dunn wrote:
> Varun,
>
> Please respond to the group. This is for everyone to have a chance to learn
> from the discussion of ideas.
>
> On Fri, Jul 23, 2010 at 2:17 AM, varoonian . wrote:
>
>> Dear Mr.Dunn,
>>
>> Yes. I noticed that the INIT bit goes back to '0' once the initialization
>> is complete in the DSK 6416. I took care to set the '*MTYPE' * in the
>> CECTL0 register as a 32-bit SDRAM before setting *INIT bit to 1.* I
>> checked the data present in the CE0 space in CCS by viewing the memory
>> content at CE0 and plotted the data just to verify.
>>
>> In your previous email you had mentioned about diving the memory into 8
>> segments.
>>
>> "Divide the memory into 8 segments and use the existing DC interface
>> signals [128MB].
>> CE2 & !DB_CNTL0 & !DB_CNTL1 = MemSpace0 [16MB ea]
>> CE2 & !DB_CNTL0 & DB_CNTL1 = MemSpace1
>> ..............................
>> ..............................
>>
>> CE3 & DB_CNTL0 & !DB_CNTL1 = MemSpace6
>> CE3 & DB_CNTL0 & DB_CNTL1 = MemSpace7" .. * Did you mean DC_CNTL ?
>> What happens when DC_CNTL0=0 and DC_CNTL_1=0 ? I do not understand that
>> part.*
>>
>
> Yes, I meant DC_CNTL.
>
> Let me explain it this way -
>
> DC furnishes A2:A21
> DC_CNTL0 = A22
> DC_CNTL1 = A23
> CE34 low [and board_enable]
> CE34 high [and board_enable]
>
> If you need more address space, you can use
>
> DC furnishes A2:A21, memory access is always done using CE3.
> CE4 writes to a latch were each bit represents A22, A23, A24, A25, A26,
> A27. You would do this write to select a particular segment/bank of memory
> before accessing.
>
> mikedunn
>> *
>> *
>> *Thanks,*
>> On Wed, Jul 21, 2010 at 11:01 PM, Michael Dunn wrote:
>>
>>> Varun,
>>>
>>> On Wed, Jul 21, 2010 at 6:17 PM, varoonian . wrote:
>>>
>>>> Dear Mr.Dunn,
>>>>
>>>> I read about the EMIF registers and the gel file which sets the memory
>>>> map for the DSK6416.
>>>>
>>>> I activated the CE0 space for SDRAM by configuring the *MTYPE* field in
>>>> the *CECTL0 register*. Is this correct ? After that initialized the
>>>> SDRAM by turning *INIT* field in the* EMIFA_SDCTL register.*
>>>>
>>>
>>> Yes, but... you need to follow the steps below. Specifically, you need to
>>> initialize all of the bits in the SDCTL register [like the GEL file does] as
>>> your last EMIF setup write.
>>>
>>> "The EMIF automatically clears the INIT field to zero after it performs
>>> SDRAM
>>> initialization. When RESET goes inactive, none of the CE spaces will be
>>> configured
>>> as SDRAM, so the INIT field will quickly change from 1 to 0. The CPU
>>> should initialize all of the CE space control registers and the SDRAM
>>> extension
>>> register before it sets the INIT bit back to 1."
>>>
>>>>
>>>> Is there a way to set the CE1space for SDRAM or Daughter Card ? .. or
>>>> is it reserved ?
>>>>
>>>
>>> I'm not sure that I understand the question, but I will try to explain
>>> 'CE spaces'.
>>> There is nothing special about 'CEn spaces', except for CE1 being enabled
>>> for booting. The four CE spaces are simply a decode of the 4 MSBs of a 32
>>> bit address.
>>> CE0-1000b
>>> CE1-1001b
>>> CE2-1010b
>>> CE3-1011b
>>> If you make a custom board, you could put SDRAM in any, all, or none of
>>> the CE spaces.
>>> The designers of the 6713 DSK have hardwired CE0 to SDRAM and CE1 to
>>> flash and on board control logic. CE2 and CE3 are hardwired to the
>>> daughtercard connector.
>>>
>>> mikedunn
>>>
>>>>
>>>> For the CSL implementation is it enough if you include the necessary CSL
>>>> header file.. for example say I want to initialise the INIT bit in
>>>> SDRAM_CTL..
>>>>
>>>> *#include*
>>>> *#include*
>>>>
>>>> void main()
>>>> {
>>>>
>>>> #define DC_REG 0x60000001
>>>>
>>>> #define EMIFA_GCTL 0x01800000
>>>> #define EMIFA_CE1 0x01800004
>>>> #define EMIFA_CE0 0x01800008
>>>> #define EMIFA_CE2 0x01800010
>>>> #define EMIFA_CE3 0x01800014
>>>> #define EMIFA_SDRAMCTL 0x01800018
>>>> /* other macros as well for the rest of the EMIFA register */
>>>>
>>>> *(int*)EMIFA_CE0 =0xFFFFFF33;
>>>>
>>>> *(int*)EMIFA_SDRAMEXT = 0x001faf4d;
>>>>
>>>> // setting INIT bit to 1 -- Initializing SDRAM //
>>>>
>>>> //*(int*)EMIFA_SDRAMCTL =0x47115000;
>>>>
>>>> /* CSL implemenation */
>>>>
>>>> *EMIFA_SDCTL_INIT_YES;*
>>>>
>>>> }
>>>>
>>>> Regards,
>>>>
>>>> Varun
>>>>
>>>>
>>>>
>>>> On Sat, Jul 10, 2010 at 2:38 PM, varoonian . wrote:
>>>>
>>>>> Thanks a lot Mr.Dunn. I'm looking into it.
>>>>>
>>>>> Regards,
>>>>>
>>>>>
>>>>> On Thu, Jul 8, 2010 at 10:06 AM, Michael Dunn >>>>> > wrote:
>>>>>
>>>>>> Varun,
>>>>>>
>>>>>> On Thu, Jul 8, 2010 at 12:42 AM, varoonian . wrote:
>>>>>>
>>>>>>> Dear Mr.Dunn,
>>>>>>>
>>>>>>> Thank you very much.
>>>>>>>
>>>>>>> I will be using the DDR RAM ( 256 MB ) on the Virtex-5 Board since
>>>>>>> the SDRAM of 16 MB on the DSK isn't sufficient.
>>>>>>>
>>>>>>
>>>>>> You may want to use the 16 MB for code/data that requires more
>>>>>> frequent access
>>>>>> I am assuming that the Virtex-5 Board will be accessed by
>>>>>> 6416_EMIF_async->DCIF_>Virtex_MemController->DDR_RAM.
>>>>>> I anticipate that this will be a much slower access path.
>>>>>>
>>>>>>>
>>>>>>> But I notice the EMIFA has only 22 address lines, which means I'll be
>>>>>>> able to access only 2^22 = approx (4MB) of external memory. How does one
>>>>>>> deal with this kind of problem ?
>>>>>>>
>>>>>>
>>>>>> Actually the device EMIFA can access 2^22 64bit locations [refer to
>>>>>> 'byte enables'].
>>>>>> Some thoughts are:
>>>>>>
>>>>>> Divide the memory into 8 segments and use the existing DC interface
>>>>>> signals [128MB].
>>>>>> CE2 & !DB_CNTL0 & !DB_CNTL1 = MemSpace0 [16MB ea]
>>>>>> CE2 & !DB_CNTL0 & DB_CNTL1 = MemSpace1
>>>>>> CE2 & DB_CNTL0 & !DB_CNTL1 = MemSpace2
>>>>>> CE2 & DB_CNTL0 & DB_CNTL1 = MemSpace3
>>>>>> CE3 & !DB_CNTL0 & !DB_CNTL1 = MemSpace4
>>>>>> CE3 & !DB_CNTL0 & DB_CNTL1 = MemSpace5
>>>>>> CE3 & DB_CNTL0 & !DB_CNTL1 = MemSpace6
>>>>>> CE3 & DB_CNTL0 & DB_CNTL1 = MemSpace7
>>>>>>
>>>>>> Always access 16MB memory 'windows' via CE2.
>>>>>> Define a single register in CE3 space that defines the high order
>>>>>> address bits [which effectively defines where the memory window is in the
>>>>>> address space.
>>>>>>
>>>>>> !!NOTE!!:
>>>>>> Any of these solutions will require some special handling in software.
>>>>>> If your application is dealing with large data sets, keep the data
>>>>>> separate from the code and ensure that each data set/buffer is contained
>>>>>> within a single memory segment/window.
>>>>>> Follow the same guidelines for your code by not letting it cross
>>>>>> segment/window boundaries.
>>>>>>
>>>>>> mikedunn
>>>>>>
>>>>>>>
>>>>>>> Thanks,
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> On Wed, Jul 7, 2010 at 6:38 PM, Michael Dunn <
>>>>>>> m...@gmail.com> wrote:
>>>>>>>
>>>>>>>> Varun,
>>>>>>>>
>>>>>>>> On Wed, Jul 7, 2010 at 1:49 AM, varoonian . wrote:
>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Hello,
>>>>>>>>>
>>>>>>>>> I need to connect the TMS320"6416" DSK to the Virtex-5 FPGA.
>>>>>>>>>
>>>>>>>>> In order to do that I need to know the *IO functionalites of the
>>>>>>>>> DSK. *
>>>>>>>>>
>>>>>>>>
>>>>>>>> If you are interested in performance and flexibility, I suggest that
>>>>>>>> you configure your FPGA as a memory mapped device [all access is by reading
>>>>>>>> and writing memory locations]. You don't need to worry about any other 'I/O'
>>>>>>>> capabilities. If you can afford it, use a 32 bit data interface [as opposed
>>>>>>>> to 16 or 8 bits].
>>>>>>>>
>>>>>>>>
>>>>>>>>> **Can anyone kindly suggest any manuals or documents to go about
>>>>>>>>> before programming the EMIF on the DSK. Programming examples will be of
>>>>>>>>> great help to me.
>>>>>>>>>
>>>>>>>>
>>>>>>>> The only EMIF programming that you will need to do is a one time
>>>>>>>> setup. Review the EMIF setup in the DSK GEL file - you may be able to use
>>>>>>>> them 'as is' or you might have to change 1 value for your application.
>>>>>>>> Check spru190.pdf and look up the 'spru' number for the EMIF manual.
>>>>>>>>
>>>>>>>>>
>>>>>>>>> Do I also need to learn about GPIO ??
>>>>>>>>>
>>>>>>>>
>>>>>>>> no.
>>>>>>>>
>>>>>>>> mikedunn
>>>>>>>>
>>>>>>>>>
>>>>>>>>> Thanks,
>>>>>>>>>
>>>>>>>>> --
>>>>>>>>> Varun
>>>>>>>>>
>>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> --
>>>>>>>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> --
>>>>>>> Varun
>>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>> --
>>>>>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>>>>>>
>>>>>
>>>>>
>>>>>
>>>>> --
>>>>> Varun
>>>>>
>>>>
>>>>
>>>>
>>>> --
>>>> Varun
>>>>
>>>
>>>
>>>
>>> --
>>> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>>> --
>> Varun
>> --
> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>
--
Varun
