Hi Everyone,
I am trying to perform data transfer form a FIFO ( on a Virtex-5 FPGA ) to
the DSK 6416 SDRAM using the Peripheral Device Transfer available on the DSK
6416.
According to XAPP753 ( Xilinx document that describes connection between
FPGA and EMIF ) PDT pin is supposed to be use for interfacing with the FPGA.
But *I am unable to find the PDT pin on the EMIFA. Is it an internal pin ?
*
*Thanks,*
--
Varun
PDT pin on the EMIF(DSK 6416)
Started by ●August 18, 2010
Reply by ●August 18, 20102010-08-18
Varun,
On 8/18/2010 12:47 PM, varoonian . wrote:
> Hi Everyone,
> I am trying to perform data transfer form a FIFO ( on a Virtex-5 FPGA
> ) to the DSK 6416 SDRAM using the Peripheral Device Transfer available
> on the DSK 6416.
> According to XAPP753 ( Xilinx document that describes connection
> between FPGA and EMIF ) PDT pin is supposed to be use for interfacing
> with the FPGA.
> But *I am unable to find the PDT pin on the EMIFA. Is it an internal
> pin ? *
>
NO.
Try the following procedure.
1. Goto ti.com and get the 6416 datasheet.
2. Open the datasheet and search for 'PDT'.
3. You will find info like:
PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS
bit to 1 in the EDMA options parameter RAM). For PDT read, data
is not latched into EMIF. The PDTRL field in the PDT control register
(PDTCTL) configures the latency of the PDT signal with respect to the data
phase of a read transaction. The latency of the PDT signal for a read
can be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10, or 11,
respectively. PDTRL equals 00 (zero latency) in Figure 27.
PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD
bit to 1 in the EDMA options parameter RAM). For PDT write, data
is not driven (in High-Z). The PDTWL field in the PDT control register
(PDTCTL) configures the latency of the PDT signal with respect to the data
phase of a write transaction. The latency of the PDT signal for a write
transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL to 00,
01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 28.
For EMIFA, EMIF Bus consists of: ACE[3:0], ABE[7:0], AED[63:0],
AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and
AAWE/ASDWE/ASWE , ASDCKE, ASOE3, and APDT.
APDT M22 O/Z IPU EMIFA peripheral data transfer, allows direct transfer
between external peripherals
mikedunn
> *Thanks,*
>
> --
> Varun
>
On 8/18/2010 12:47 PM, varoonian . wrote:
> Hi Everyone,
> I am trying to perform data transfer form a FIFO ( on a Virtex-5 FPGA
> ) to the DSK 6416 SDRAM using the Peripheral Device Transfer available
> on the DSK 6416.
> According to XAPP753 ( Xilinx document that describes connection
> between FPGA and EMIF ) PDT pin is supposed to be use for interfacing
> with the FPGA.
> But *I am unable to find the PDT pin on the EMIFA. Is it an internal
> pin ? *
>
NO.
Try the following procedure.
1. Goto ti.com and get the 6416 datasheet.
2. Open the datasheet and search for 'PDT'.
3. You will find info like:
PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS
bit to 1 in the EDMA options parameter RAM). For PDT read, data
is not latched into EMIF. The PDTRL field in the PDT control register
(PDTCTL) configures the latency of the PDT signal with respect to the data
phase of a read transaction. The latency of the PDT signal for a read
can be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10, or 11,
respectively. PDTRL equals 00 (zero latency) in Figure 27.
PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD
bit to 1 in the EDMA options parameter RAM). For PDT write, data
is not driven (in High-Z). The PDTWL field in the PDT control register
(PDTCTL) configures the latency of the PDT signal with respect to the data
phase of a write transaction. The latency of the PDT signal for a write
transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL to 00,
01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 28.
For EMIFA, EMIF Bus consists of: ACE[3:0], ABE[7:0], AED[63:0],
AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and
AAWE/ASDWE/ASWE , ASDCKE, ASOE3, and APDT.
APDT M22 O/Z IPU EMIFA peripheral data transfer, allows direct transfer
between external peripherals
mikedunn
> *Thanks,*
>
> --
> Varun
>
Reply by ●August 18, 20102010-08-18
I found the pins.
They are given below
The two MST address lines are used as extra control lines during a PDT
transaction:
♦ PDTA (PDT access)
Depending on the bus width, PDTA is EA19 (64 bits), EA18 (32 bits), or EA17
(16
bits).
♦ PDTD (PDT direction)
Depending on the bus width, PDTD is EA20 (64 bits), EA19 (32 bits), or EA18
(16
bits).
Thanks,
On Wed, Aug 18, 2010 at 10:47 AM, varoonian . wrote:
>
> Hi Everyone,
> I am trying to perform data transfer form a FIFO ( on a Virtex-5 FPGA ) to
> the DSK 6416 SDRAM using the Peripheral Device Transfer available on the DSK
> 6416.
> According to XAPP753 ( Xilinx document that describes connection between
> FPGA and EMIF ) PDT pin is supposed to be use for interfacing with the FPGA.
> But *I am unable to find the PDT pin on the EMIFA. Is it an internal pin
> ? *
> *Thanks,*
> --
> Varun
>
--
Varun
They are given below
The two MST address lines are used as extra control lines during a PDT
transaction:
♦ PDTA (PDT access)
Depending on the bus width, PDTA is EA19 (64 bits), EA18 (32 bits), or EA17
(16
bits).
♦ PDTD (PDT direction)
Depending on the bus width, PDTD is EA20 (64 bits), EA19 (32 bits), or EA18
(16
bits).
Thanks,
On Wed, Aug 18, 2010 at 10:47 AM, varoonian . wrote:
>
> Hi Everyone,
> I am trying to perform data transfer form a FIFO ( on a Virtex-5 FPGA ) to
> the DSK 6416 SDRAM using the Peripheral Device Transfer available on the DSK
> 6416.
> According to XAPP753 ( Xilinx document that describes connection between
> FPGA and EMIF ) PDT pin is supposed to be use for interfacing with the FPGA.
> But *I am unable to find the PDT pin on the EMIFA. Is it an internal pin
> ? *
> *Thanks,*
> --
> Varun
>
--
Varun
Reply by ●August 20, 20102010-08-20
Thank you Mr.Dunn. PDTA abd PDTB are the signals corresponding to the
respective EMIF(s).
On Wed, Aug 18, 2010 at 3:31 PM, mikedunn wrote:
> Varun,
> On 8/18/2010 12:47 PM, varoonian . wrote:
> Hi Everyone,
> I am trying to perform data transfer form a FIFO ( on a Virtex-5 FPGA )
> to the DSK 6416 SDRAM using the Peripheral Device Transfer available on the
> DSK 6416.
> According to XAPP753 ( Xilinx document that describes connection between
> FPGA and EMIF ) PDT pin is supposed to be use for interfacing with the FPGA.
> But *I am unable to find the PDT pin on the EMIFA. Is it an internal pin
> ? *
>
>
> NO.
> Try the following procedure.
> 1. Goto ti.com and get the 6416 datasheet.
> 2. Open the datasheet and search for 'PDT'.
> 3. You will find info like:
> PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit
> to 1 in the EDMA options parameter RAM). For PDT read, data
> is not latched into EMIF. The PDTRL field in the PDT control register
> (PDTCTL) configures the latency of the PDT signal with respect to the data
> phase of a read transaction. The latency of the PDT signal for a read can
> be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10, or 11,
> respectively. PDTRL equals 00 (zero latency) in Figure 27.
>
> PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit
> to 1 in the EDMA options parameter RAM). For PDT write, data
> is not driven (in High-Z). The PDTWL field in the PDT control register
> (PDTCTL) configures the latency of the PDT signal with respect to the data
> phase of a write transaction. The latency of the PDT signal for a write
> transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL to 00,
> 01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 28.
>
> For EMIFA, EMIF Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3],
> AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and
> AAWE/ASDWE/ASWE , ASDCKE, ASOE3, and APDT.
>
> APDT M22 O/Z IPU EMIFA peripheral data transfer, allows direct transfer
> between external peripherals
>
> mikedunn
> *Thanks,*
> --
> Varun
>
>
--
Varun
respective EMIF(s).
On Wed, Aug 18, 2010 at 3:31 PM, mikedunn wrote:
> Varun,
> On 8/18/2010 12:47 PM, varoonian . wrote:
> Hi Everyone,
> I am trying to perform data transfer form a FIFO ( on a Virtex-5 FPGA )
> to the DSK 6416 SDRAM using the Peripheral Device Transfer available on the
> DSK 6416.
> According to XAPP753 ( Xilinx document that describes connection between
> FPGA and EMIF ) PDT pin is supposed to be use for interfacing with the FPGA.
> But *I am unable to find the PDT pin on the EMIFA. Is it an internal pin
> ? *
>
>
> NO.
> Try the following procedure.
> 1. Goto ti.com and get the 6416 datasheet.
> 2. Open the datasheet and search for 'PDT'.
> 3. You will find info like:
> PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit
> to 1 in the EDMA options parameter RAM). For PDT read, data
> is not latched into EMIF. The PDTRL field in the PDT control register
> (PDTCTL) configures the latency of the PDT signal with respect to the data
> phase of a read transaction. The latency of the PDT signal for a read can
> be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10, or 11,
> respectively. PDTRL equals 00 (zero latency) in Figure 27.
>
> PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit
> to 1 in the EDMA options parameter RAM). For PDT write, data
> is not driven (in High-Z). The PDTWL field in the PDT control register
> (PDTCTL) configures the latency of the PDT signal with respect to the data
> phase of a write transaction. The latency of the PDT signal for a write
> transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL to 00,
> 01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 28.
>
> For EMIFA, EMIF Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3],
> AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and
> AAWE/ASDWE/ASWE , ASDCKE, ASOE3, and APDT.
>
> APDT M22 O/Z IPU EMIFA peripheral data transfer, allows direct transfer
> between external peripherals
>
> mikedunn
> *Thanks,*
> --
> Varun
>
>
--
Varun
Reply by ●August 23, 20102010-08-23
Dear Mr. Dunn,
Regarding the EDMA controller, does it consider EXT_INT pin ( either pin 4
,5,6, or 7 ) as an external event to perform a PDT write from an external
FIFO to SDRAM. I am going to connect the FIFO Almost_full flag to the
EXT_INT. ( for my initial design testing )
How do you read this EXT_INT pin ? Is it by checking whether the
corresponding bit of the Interrupt Flag Register ( IFR ) is set ?
Thanks,
Varun
On Fri, Aug 20, 2010 at 1:43 PM, varoonian . wrote:
> Thank you Mr.Dunn. PDTA abd PDTB are the signals corresponding to the
> respective EMIF(s).
> On Wed, Aug 18, 2010 at 3:31 PM, mikedunn wrote:
>
>> Varun,
>> On 8/18/2010 12:47 PM, varoonian . wrote:
>> Hi Everyone,
>> I am trying to perform data transfer form a FIFO ( on a Virtex-5 FPGA )
>> to the DSK 6416 SDRAM using the Peripheral Device Transfer available on the
>> DSK 6416.
>> According to XAPP753 ( Xilinx document that describes connection between
>> FPGA and EMIF ) PDT pin is supposed to be use for interfacing with the FPGA.
>> But *I am unable to find the PDT pin on the EMIFA. Is it an internal
>> pin ? *
>>
>>
>> NO.
>> Try the following procedure.
>> 1. Goto ti.com and get the 6416 datasheet.
>> 2. Open the datasheet and search for 'PDT'.
>> 3. You will find info like:
>> PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit
>> to 1 in the EDMA options parameter RAM). For PDT read, data
>> is not latched into EMIF. The PDTRL field in the PDT control register
>> (PDTCTL) configures the latency of the PDT signal with respect to the data
>> phase of a read transaction. The latency of the PDT signal for a read can
>> be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10, or 11,
>> respectively. PDTRL equals 00 (zero latency) in Figure 27.
>>
>> PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit
>> to 1 in the EDMA options parameter RAM). For PDT write, data
>> is not driven (in High-Z). The PDTWL field in the PDT control register
>> (PDTCTL) configures the latency of the PDT signal with respect to the data
>> phase of a write transaction. The latency of the PDT signal for a write
>> transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL to 00,
>> 01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 28.
>>
>> For EMIFA, EMIF Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3],
>> AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and
>> AAWE/ASDWE/ASWE , ASDCKE, ASOE3, and APDT.
>>
>> APDT M22 O/Z IPU EMIFA peripheral data transfer, allows direct transfer
>> between external peripherals
>>
>> mikedunn
>> *Thanks,*
>> --
>> Varun
>>
>>
> --
> Varun
>
--
Varun
Regarding the EDMA controller, does it consider EXT_INT pin ( either pin 4
,5,6, or 7 ) as an external event to perform a PDT write from an external
FIFO to SDRAM. I am going to connect the FIFO Almost_full flag to the
EXT_INT. ( for my initial design testing )
How do you read this EXT_INT pin ? Is it by checking whether the
corresponding bit of the Interrupt Flag Register ( IFR ) is set ?
Thanks,
Varun
On Fri, Aug 20, 2010 at 1:43 PM, varoonian . wrote:
> Thank you Mr.Dunn. PDTA abd PDTB are the signals corresponding to the
> respective EMIF(s).
> On Wed, Aug 18, 2010 at 3:31 PM, mikedunn wrote:
>
>> Varun,
>> On 8/18/2010 12:47 PM, varoonian . wrote:
>> Hi Everyone,
>> I am trying to perform data transfer form a FIFO ( on a Virtex-5 FPGA )
>> to the DSK 6416 SDRAM using the Peripheral Device Transfer available on the
>> DSK 6416.
>> According to XAPP753 ( Xilinx document that describes connection between
>> FPGA and EMIF ) PDT pin is supposed to be use for interfacing with the FPGA.
>> But *I am unable to find the PDT pin on the EMIFA. Is it an internal
>> pin ? *
>>
>>
>> NO.
>> Try the following procedure.
>> 1. Goto ti.com and get the 6416 datasheet.
>> 2. Open the datasheet and search for 'PDT'.
>> 3. You will find info like:
>> PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit
>> to 1 in the EDMA options parameter RAM). For PDT read, data
>> is not latched into EMIF. The PDTRL field in the PDT control register
>> (PDTCTL) configures the latency of the PDT signal with respect to the data
>> phase of a read transaction. The latency of the PDT signal for a read can
>> be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10, or 11,
>> respectively. PDTRL equals 00 (zero latency) in Figure 27.
>>
>> PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit
>> to 1 in the EDMA options parameter RAM). For PDT write, data
>> is not driven (in High-Z). The PDTWL field in the PDT control register
>> (PDTCTL) configures the latency of the PDT signal with respect to the data
>> phase of a write transaction. The latency of the PDT signal for a write
>> transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL to 00,
>> 01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 28.
>>
>> For EMIFA, EMIF Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3],
>> AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and
>> AAWE/ASDWE/ASWE , ASDCKE, ASOE3, and APDT.
>>
>> APDT M22 O/Z IPU EMIFA peripheral data transfer, allows direct transfer
>> between external peripherals
>>
>> mikedunn
>> *Thanks,*
>> --
>> Varun
>>
>>
> --
> Varun
>
--
Varun
