Hello Everyone,
I am trying to do a Peripheral Device Transfer ( a PDT write by programming
the EDMA and EMIFA registers ) from a FIFO on a Virtex-5 FPGA to a DSK6416
SDRAM.
My question is, when I look at the EMIF out clock ( ECLKOUT) on the scope it
DOES NOT look like a square wave but rather like a sinusoidal wave with a
frequency of 125 MHz and amplitude is 1.6 V.
Isn't ECLKOUT supposed to look like a square wave. I also grounded pin 75
of
J3 in the Peripheral Expansion Connector to GND.
Regards,
--
Varun
EMIF CLOCK - ECLKOUT
Started by ●June 22, 2011
Reply by ●June 22, 20112011-06-22
Varun-
> I am trying to do a Peripheral Device Transfer ( a PDT write by programming
> the EDMA and EMIFA registers ) from a FIFO on a Virtex-5 FPGA to a DSK6416
> SDRAM.
>
> My question is, when I look at the EMIF out clock ( ECLKOUT) on the scope it
> DOES NOT look like a square wave but rather like a sinusoidal wave with a
> frequency of 125 MHz and amplitude is 1.6 V.
>
> Isn't ECLKOUT supposed to look like a square wave. I also grounded pin 75 of
> J3 in the Peripheral Expansion Connector to GND.
How good is your scope? Are you using "active probes" (high-impedance, very low capacitance) ? If not, the mere act
of touching your signal with passive probes could make it look as you describe. Suggest to Google "Heisenberg
Uncertainty Principle" :-) While 125 MHz is not exactly quantum mechanics, I expect it's still substantially faster
than what you dealt with in your EE lab classes.
-Jeff
_____________________________________
> I am trying to do a Peripheral Device Transfer ( a PDT write by programming
> the EDMA and EMIFA registers ) from a FIFO on a Virtex-5 FPGA to a DSK6416
> SDRAM.
>
> My question is, when I look at the EMIF out clock ( ECLKOUT) on the scope it
> DOES NOT look like a square wave but rather like a sinusoidal wave with a
> frequency of 125 MHz and amplitude is 1.6 V.
>
> Isn't ECLKOUT supposed to look like a square wave. I also grounded pin 75 of
> J3 in the Peripheral Expansion Connector to GND.
How good is your scope? Are you using "active probes" (high-impedance, very low capacitance) ? If not, the mere act
of touching your signal with passive probes could make it look as you describe. Suggest to Google "Heisenberg
Uncertainty Principle" :-) While 125 MHz is not exactly quantum mechanics, I expect it's still substantially faster
than what you dealt with in your EE lab classes.
-Jeff
_____________________________________
Reply by ●June 22, 20112011-06-22
Varun,
On 6/22/2011 9:55 AM, Jeff Brower wrote:
>
> Varun-
>
> > I am trying to do a Peripheral Device Transfer ( a PDT write by
> programming
> > the EDMA and EMIFA registers ) from a FIFO on a Virtex-5 FPGA to a
> DSK6416
> > SDRAM.
> >
> > My question is, when I look at the EMIF out clock ( ECLKOUT) on the
> scope it
> > DOES NOT look like a square wave but rather like a sinusoidal wave
> with a
> > frequency of 125 MHz and amplitude is 1.6 V.
> >
> > Isn't ECLKOUT supposed to look like a square wave. I also grounded
> pin 75 of
> > J3 in the Peripheral Expansion Connector to GND.
>
> How good is your scope? Are you using "active probes" (high-impedance,
> very low capacitance) ? If not, the mere act
> of touching your signal with passive probes could make it look as you
> describe. Suggest to Google "Heisenberg
> Uncertainty Principle" :-) While 125 MHz is not exactly quantum
> mechanics, I expect it's still substantially faster
> than what you dealt with in your EE lab classes.
>
If your scope and probes are good to display a 125 Mhz square wave, you
may have too much capacitance on that signal line.
Are you using a wire/cable DCard bus?? If so, how long is it??
Or is your FPGA plugged directly into the DCard connector??
mikedunn
> -Jeff
On 6/22/2011 9:55 AM, Jeff Brower wrote:
>
> Varun-
>
> > I am trying to do a Peripheral Device Transfer ( a PDT write by
> programming
> > the EDMA and EMIFA registers ) from a FIFO on a Virtex-5 FPGA to a
> DSK6416
> > SDRAM.
> >
> > My question is, when I look at the EMIF out clock ( ECLKOUT) on the
> scope it
> > DOES NOT look like a square wave but rather like a sinusoidal wave
> with a
> > frequency of 125 MHz and amplitude is 1.6 V.
> >
> > Isn't ECLKOUT supposed to look like a square wave. I also grounded
> pin 75 of
> > J3 in the Peripheral Expansion Connector to GND.
>
> How good is your scope? Are you using "active probes" (high-impedance,
> very low capacitance) ? If not, the mere act
> of touching your signal with passive probes could make it look as you
> describe. Suggest to Google "Heisenberg
> Uncertainty Principle" :-) While 125 MHz is not exactly quantum
> mechanics, I expect it's still substantially faster
> than what you dealt with in your EE lab classes.
>
If your scope and probes are good to display a 125 Mhz square wave, you
may have too much capacitance on that signal line.
Are you using a wire/cable DCard bus?? If so, how long is it??
Or is your FPGA plugged directly into the DCard connector??
mikedunn
> -Jeff
Reply by ●June 22, 20112011-06-22
Varun-
> I am using a Tektronix TAP 1500 (1.5 GHz Active Probe and less than 1pF
> input capacitance).
>
> I am using a Tektronix DPO 7254 2.5GHz oscilloscope.
Scope and probes sound fine. Can you slow down the clock? If a 25 MHz clock looks Ok, then you might suspect
excessive line length or other sources of loading, as Mike suggested.
-Jeff
> On Wed, Jun 22, 2011 at 8:19 AM, mikedunn wrote:
>
>> **
>> Varun,
>> On 6/22/2011 9:55 AM, Jeff Brower wrote:
>>
>> Varun-
>>
>> > I am trying to do a Peripheral Device Transfer ( a PDT write by
>> programming
>> > the EDMA and EMIFA registers ) from a FIFO on a Virtex-5 FPGA to a
>> DSK6416
>> > SDRAM.
>> >
>> > My question is, when I look at the EMIF out clock ( ECLKOUT) on the scope
>> it
>> > DOES NOT look like a square wave but rather like a sinusoidal wave with a
>> > frequency of 125 MHz and amplitude is 1.6 V.
>> >
>> > Isn't ECLKOUT supposed to look like a square wave. I also grounded pin 75
>> of
>> > J3 in the Peripheral Expansion Connector to GND.
>>
>> How good is your scope? Are you using "active probes" (high-impedance, very
>> low capacitance) ? If not, the mere act
>> of touching your signal with passive probes could make it look as you
>> describe. Suggest to Google "Heisenberg
>> Uncertainty Principle" :-) While 125 MHz is not exactly quantum mechanics,
>> I expect it's still substantially faster
>> than what you dealt with in your EE lab classes.
>>
>>
>> If your scope and probes are good to display a 125 Mhz square wave, you may
>> have too much capacitance on that signal line.
>> Are you using a wire/cable DCard bus?? If so, how long is it??
>> Or is your FPGA plugged directly into the DCard connector??
>>
>> mikedunn
>> -Jeff
>>
>>
> --
> Varun
>
_____________________________________
> I am using a Tektronix TAP 1500 (1.5 GHz Active Probe and less than 1pF
> input capacitance).
>
> I am using a Tektronix DPO 7254 2.5GHz oscilloscope.
Scope and probes sound fine. Can you slow down the clock? If a 25 MHz clock looks Ok, then you might suspect
excessive line length or other sources of loading, as Mike suggested.
-Jeff
> On Wed, Jun 22, 2011 at 8:19 AM, mikedunn wrote:
>
>> **
>> Varun,
>> On 6/22/2011 9:55 AM, Jeff Brower wrote:
>>
>> Varun-
>>
>> > I am trying to do a Peripheral Device Transfer ( a PDT write by
>> programming
>> > the EDMA and EMIFA registers ) from a FIFO on a Virtex-5 FPGA to a
>> DSK6416
>> > SDRAM.
>> >
>> > My question is, when I look at the EMIF out clock ( ECLKOUT) on the scope
>> it
>> > DOES NOT look like a square wave but rather like a sinusoidal wave with a
>> > frequency of 125 MHz and amplitude is 1.6 V.
>> >
>> > Isn't ECLKOUT supposed to look like a square wave. I also grounded pin 75
>> of
>> > J3 in the Peripheral Expansion Connector to GND.
>>
>> How good is your scope? Are you using "active probes" (high-impedance, very
>> low capacitance) ? If not, the mere act
>> of touching your signal with passive probes could make it look as you
>> describe. Suggest to Google "Heisenberg
>> Uncertainty Principle" :-) While 125 MHz is not exactly quantum mechanics,
>> I expect it's still substantially faster
>> than what you dealt with in your EE lab classes.
>>
>>
>> If your scope and probes are good to display a 125 Mhz square wave, you may
>> have too much capacitance on that signal line.
>> Are you using a wire/cable DCard bus?? If so, how long is it??
>> Or is your FPGA plugged directly into the DCard connector??
>>
>> mikedunn
>> -Jeff
>>
>>
> --
> Varun
>
_____________________________________
Reply by ●June 22, 20112011-06-22
Varun-
> On the DSK 6416T, the minimum I can reduce the EMIF frequency is to 100 MHz.
> by changing the configuration switches on the DSK6416.
>
> I am not sure how to connect an external clock to the EMIF's ECLKIN. The
> EMIF connector does not have an ECLKIN pin on it.
With C64x, you can configure ECLKIN to be CLKOUT4 or CLKOUT6 (CPU clock /4 and /6). You should be able to adjust CPU
frequency to be low, for example temporarily mod the CLKMODEn pull-up (or pull-down) Rs on the DSK board. Maybe the
easiest thing is just to temporarily put a jumper wire on both of those to ground, bypassing the Rs... as I recall, a
value of 00 = bypass (no PLL multiplier).
-Jeff
> On Wed, Jun 22, 2011 at 12:47 PM, Jeff Brower wrote:
>
>> Varun-
>>
>> > I am using a Tektronix TAP 1500 (1.5 GHz Active Probe and less than 1pF
>> > input capacitance).
>> >
>> > I am using a Tektronix DPO 7254 2.5GHz oscilloscope.
>>
>> Scope and probes sound fine. Can you slow down the clock? If a 25 MHz
>> clock looks Ok, then you might suspect
>> excessive line length or other sources of loading, as Mike suggested.
>>
>> -Jeff
>>
>> > On Wed, Jun 22, 2011 at 8:19 AM, mikedunn
>> wrote:
>> >
>> >> **
>> >> Varun,
>> >>
>> >>
>> >> On 6/22/2011 9:55 AM, Jeff Brower wrote:
>> >>
>> >>
>> >>
>> >> Varun-
>> >>
>> >> > I am trying to do a Peripheral Device Transfer ( a PDT write by
>> >> programming
>> >> > the EDMA and EMIFA registers ) from a FIFO on a Virtex-5 FPGA to a
>> >> DSK6416
>> >> > SDRAM.
>> >> >
>> >> > My question is, when I look at the EMIF out clock ( ECLKOUT) on the
>> scope
>> >> it
>> >> > DOES NOT look like a square wave but rather like a sinusoidal wave
>> with a
>> >> > frequency of 125 MHz and amplitude is 1.6 V.
>> >> >
>> >> > Isn't ECLKOUT supposed to look like a square wave. I also grounded pin
>> 75
>> >> of
>> >> > J3 in the Peripheral Expansion Connector to GND.
>> >>
>> >> How good is your scope? Are you using "active probes" (high-impedance,
>> very
>> >> low capacitance) ? If not, the mere act
>> >> of touching your signal with passive probes could make it look as you
>> >> describe. Suggest to Google "Heisenberg
>> >> Uncertainty Principle" :-) While 125 MHz is not exactly quantum
>> mechanics,
>> >> I expect it's still substantially faster
>> >> than what you dealt with in your EE lab classes.
>> >>
>> >>
>> >> If your scope and probes are good to display a 125 Mhz square wave, you
>> may
>> >> have too much capacitance on that signal line.
>> >> Are you using a wire/cable DCard bus?? If so, how long is it??
>> >> Or is your FPGA plugged directly into the DCard connector??
>> >>
>> >> mikedunn
>> >>
>> >>
>> >> -Jeff
>> >>
>> >>
>> >>
>> >>
>> >
>> >
>> > --
>> > Varun
>> >
> --
> Varun
>
_____________________________________
> On the DSK 6416T, the minimum I can reduce the EMIF frequency is to 100 MHz.
> by changing the configuration switches on the DSK6416.
>
> I am not sure how to connect an external clock to the EMIF's ECLKIN. The
> EMIF connector does not have an ECLKIN pin on it.
With C64x, you can configure ECLKIN to be CLKOUT4 or CLKOUT6 (CPU clock /4 and /6). You should be able to adjust CPU
frequency to be low, for example temporarily mod the CLKMODEn pull-up (or pull-down) Rs on the DSK board. Maybe the
easiest thing is just to temporarily put a jumper wire on both of those to ground, bypassing the Rs... as I recall, a
value of 00 = bypass (no PLL multiplier).
-Jeff
> On Wed, Jun 22, 2011 at 12:47 PM, Jeff Brower wrote:
>
>> Varun-
>>
>> > I am using a Tektronix TAP 1500 (1.5 GHz Active Probe and less than 1pF
>> > input capacitance).
>> >
>> > I am using a Tektronix DPO 7254 2.5GHz oscilloscope.
>>
>> Scope and probes sound fine. Can you slow down the clock? If a 25 MHz
>> clock looks Ok, then you might suspect
>> excessive line length or other sources of loading, as Mike suggested.
>>
>> -Jeff
>>
>> > On Wed, Jun 22, 2011 at 8:19 AM, mikedunn
>> wrote:
>> >
>> >> **
>> >> Varun,
>> >>
>> >>
>> >> On 6/22/2011 9:55 AM, Jeff Brower wrote:
>> >>
>> >>
>> >>
>> >> Varun-
>> >>
>> >> > I am trying to do a Peripheral Device Transfer ( a PDT write by
>> >> programming
>> >> > the EDMA and EMIFA registers ) from a FIFO on a Virtex-5 FPGA to a
>> >> DSK6416
>> >> > SDRAM.
>> >> >
>> >> > My question is, when I look at the EMIF out clock ( ECLKOUT) on the
>> scope
>> >> it
>> >> > DOES NOT look like a square wave but rather like a sinusoidal wave
>> with a
>> >> > frequency of 125 MHz and amplitude is 1.6 V.
>> >> >
>> >> > Isn't ECLKOUT supposed to look like a square wave. I also grounded pin
>> 75
>> >> of
>> >> > J3 in the Peripheral Expansion Connector to GND.
>> >>
>> >> How good is your scope? Are you using "active probes" (high-impedance,
>> very
>> >> low capacitance) ? If not, the mere act
>> >> of touching your signal with passive probes could make it look as you
>> >> describe. Suggest to Google "Heisenberg
>> >> Uncertainty Principle" :-) While 125 MHz is not exactly quantum
>> mechanics,
>> >> I expect it's still substantially faster
>> >> than what you dealt with in your EE lab classes.
>> >>
>> >>
>> >> If your scope and probes are good to display a 125 Mhz square wave, you
>> may
>> >> have too much capacitance on that signal line.
>> >> Are you using a wire/cable DCard bus?? If so, how long is it??
>> >> Or is your FPGA plugged directly into the DCard connector??
>> >>
>> >> mikedunn
>> >>
>> >>
>> >> -Jeff
>> >>
>> >>
>> >>
>> >>
>> >
>> >
>> > --
>> > Varun
>> >
> --
> Varun
>
_____________________________________
Reply by ●June 23, 20112011-06-23
Hello Mike,
I haven't plugged in the FPGA directly, I have used ribbon cables and
soldered its other end to a Samtec 80-pin break out panel that sits on the
EMIF. ( http://www.link-research.com/index.php?main_page=popup_image&pID6
).
Regards,
On Wed, Jun 22, 2011 at 9:34 AM, varoonian . wrote:
> Hello Mike and Jeff,
>
> I am using a Tektronix TAP 1500 (1.5 GHz Active Probe and less than 1pF
> input capacitance).
>
> I am using a Tektronix DPO 7254 2.5GHz oscilloscope.
>
> Regards,
> On Wed, Jun 22, 2011 at 8:19 AM, mikedunn wrote:
>
>> **
>> Varun,
>> On 6/22/2011 9:55 AM, Jeff Brower wrote:
>>
>> Varun-
>>
>> > I am trying to do a Peripheral Device Transfer ( a PDT write by
>> programming
>> > the EDMA and EMIFA registers ) from a FIFO on a Virtex-5 FPGA to a
>> DSK6416
>> > SDRAM.
>> >
>> > My question is, when I look at the EMIF out clock ( ECLKOUT) on the
>> scope it
>> > DOES NOT look like a square wave but rather like a sinusoidal wave with
>> a
>> > frequency of 125 MHz and amplitude is 1.6 V.
>> >
>> > Isn't ECLKOUT supposed to look like a square wave. I also grounded pin
>> 75 of
>> > J3 in the Peripheral Expansion Connector to GND.
>>
>> How good is your scope? Are you using "active probes" (high-impedance,
>> very low capacitance) ? If not, the mere act
>> of touching your signal with passive probes could make it look as you
>> describe. Suggest to Google "Heisenberg
>> Uncertainty Principle" :-) While 125 MHz is not exactly quantum mechanics,
>> I expect it's still substantially faster
>> than what you dealt with in your EE lab classes.
>>
>>
>> If your scope and probes are good to display a 125 Mhz square wave, you
>> may have too much capacitance on that signal line.
>> Are you using a wire/cable DCard bus?? If so, how long is it??
>> Or is your FPGA plugged directly into the DCard connector??
>>
>> mikedunn
>> -Jeff
>>
>>
> --
> Varun
>
--
Varun
I haven't plugged in the FPGA directly, I have used ribbon cables and
soldered its other end to a Samtec 80-pin break out panel that sits on the
EMIF. ( http://www.link-research.com/index.php?main_page=popup_image&pID6
).
Regards,
On Wed, Jun 22, 2011 at 9:34 AM, varoonian . wrote:
> Hello Mike and Jeff,
>
> I am using a Tektronix TAP 1500 (1.5 GHz Active Probe and less than 1pF
> input capacitance).
>
> I am using a Tektronix DPO 7254 2.5GHz oscilloscope.
>
> Regards,
> On Wed, Jun 22, 2011 at 8:19 AM, mikedunn wrote:
>
>> **
>> Varun,
>> On 6/22/2011 9:55 AM, Jeff Brower wrote:
>>
>> Varun-
>>
>> > I am trying to do a Peripheral Device Transfer ( a PDT write by
>> programming
>> > the EDMA and EMIFA registers ) from a FIFO on a Virtex-5 FPGA to a
>> DSK6416
>> > SDRAM.
>> >
>> > My question is, when I look at the EMIF out clock ( ECLKOUT) on the
>> scope it
>> > DOES NOT look like a square wave but rather like a sinusoidal wave with
>> a
>> > frequency of 125 MHz and amplitude is 1.6 V.
>> >
>> > Isn't ECLKOUT supposed to look like a square wave. I also grounded pin
>> 75 of
>> > J3 in the Peripheral Expansion Connector to GND.
>>
>> How good is your scope? Are you using "active probes" (high-impedance,
>> very low capacitance) ? If not, the mere act
>> of touching your signal with passive probes could make it look as you
>> describe. Suggest to Google "Heisenberg
>> Uncertainty Principle" :-) While 125 MHz is not exactly quantum mechanics,
>> I expect it's still substantially faster
>> than what you dealt with in your EE lab classes.
>>
>>
>> If your scope and probes are good to display a 125 Mhz square wave, you
>> may have too much capacitance on that signal line.
>> Are you using a wire/cable DCard bus?? If so, how long is it??
>> Or is your FPGA plugged directly into the DCard connector??
>>
>> mikedunn
>> -Jeff
>>
>>
> --
> Varun
>
--
Varun
Reply by ●June 23, 20112011-06-23
Hello Mike and Jeff,
I am using a Tektronix TAP 1500 (1.5 GHz Active Probe and less than 1pF
input capacitance).
I am using a Tektronix DPO 7254 2.5GHz oscilloscope.
Regards,
On Wed, Jun 22, 2011 at 8:19 AM, mikedunn wrote:
> **
> Varun,
> On 6/22/2011 9:55 AM, Jeff Brower wrote:
>
> Varun-
>
> > I am trying to do a Peripheral Device Transfer ( a PDT write by
> programming
> > the EDMA and EMIFA registers ) from a FIFO on a Virtex-5 FPGA to a
> DSK6416
> > SDRAM.
> >
> > My question is, when I look at the EMIF out clock ( ECLKOUT) on the scope
> it
> > DOES NOT look like a square wave but rather like a sinusoidal wave with a
> > frequency of 125 MHz and amplitude is 1.6 V.
> >
> > Isn't ECLKOUT supposed to look like a square wave. I also grounded pin 75
> of
> > J3 in the Peripheral Expansion Connector to GND.
>
> How good is your scope? Are you using "active probes" (high-impedance, very
> low capacitance) ? If not, the mere act
> of touching your signal with passive probes could make it look as you
> describe. Suggest to Google "Heisenberg
> Uncertainty Principle" :-) While 125 MHz is not exactly quantum mechanics,
> I expect it's still substantially faster
> than what you dealt with in your EE lab classes.
>
>
> If your scope and probes are good to display a 125 Mhz square wave, you may
> have too much capacitance on that signal line.
> Are you using a wire/cable DCard bus?? If so, how long is it??
> Or is your FPGA plugged directly into the DCard connector??
>
> mikedunn
> -Jeff
>
>
--
Varun
I am using a Tektronix TAP 1500 (1.5 GHz Active Probe and less than 1pF
input capacitance).
I am using a Tektronix DPO 7254 2.5GHz oscilloscope.
Regards,
On Wed, Jun 22, 2011 at 8:19 AM, mikedunn wrote:
> **
> Varun,
> On 6/22/2011 9:55 AM, Jeff Brower wrote:
>
> Varun-
>
> > I am trying to do a Peripheral Device Transfer ( a PDT write by
> programming
> > the EDMA and EMIFA registers ) from a FIFO on a Virtex-5 FPGA to a
> DSK6416
> > SDRAM.
> >
> > My question is, when I look at the EMIF out clock ( ECLKOUT) on the scope
> it
> > DOES NOT look like a square wave but rather like a sinusoidal wave with a
> > frequency of 125 MHz and amplitude is 1.6 V.
> >
> > Isn't ECLKOUT supposed to look like a square wave. I also grounded pin 75
> of
> > J3 in the Peripheral Expansion Connector to GND.
>
> How good is your scope? Are you using "active probes" (high-impedance, very
> low capacitance) ? If not, the mere act
> of touching your signal with passive probes could make it look as you
> describe. Suggest to Google "Heisenberg
> Uncertainty Principle" :-) While 125 MHz is not exactly quantum mechanics,
> I expect it's still substantially faster
> than what you dealt with in your EE lab classes.
>
>
> If your scope and probes are good to display a 125 Mhz square wave, you may
> have too much capacitance on that signal line.
> Are you using a wire/cable DCard bus?? If so, how long is it??
> Or is your FPGA plugged directly into the DCard connector??
>
> mikedunn
> -Jeff
>
>
--
Varun
Reply by ●June 23, 20112011-06-23
Thanks Jeff. I found those R's. They are in a resistor divider
combination
with the one unpopulated (for each CLKMODE ).
So, if I bypass those two and make them '00', does that make ECLKIN CLKOUT4 which is eventually ECLKOUT (the EMIF out clock) ??
Thanks,
I also noticed that this is going to reduce the CPU clock speed from 1 GHz
to 100 MHz.
On Wed, Jun 22, 2011 at 3:07 PM, Jeff Brower wrote:
> Varun-
>
> > On the DSK 6416T, the minimum I can reduce the EMIF frequency is to 100
> MHz.
> > by changing the configuration switches on the DSK6416.
> >
> > I am not sure how to connect an external clock to the EMIF's ECLKIN. The
> > EMIF connector does not have an ECLKIN pin on it.
>
> With C64x, you can configure ECLKIN to be CLKOUT4 or CLKOUT6 (CPU clock /4
> and /6). You should be able to adjust CPU
> frequency to be low, for example temporarily mod the CLKMODEn pull-up (or
> pull-down) Rs on the DSK board. Maybe the
> easiest thing is just to temporarily put a jumper wire on both of those to
> ground, bypassing the Rs... as I recall, a
> value of 00 = bypass (no PLL multiplier).
>
> -Jeff
>
> > On Wed, Jun 22, 2011 at 12:47 PM, Jeff Brower > >wrote:
> >
> >> Varun-
> >>
> >> > I am using a Tektronix TAP 1500 (1.5 GHz Active Probe and less than
> 1pF
> >> > input capacitance).
> >> >
> >> > I am using a Tektronix DPO 7254 2.5GHz oscilloscope.
> >>
> >> Scope and probes sound fine. Can you slow down the clock? If a 25 MHz
> >> clock looks Ok, then you might suspect
> >> excessive line length or other sources of loading, as Mike suggested.
> >>
> >> -Jeff
> >>
> >> > On Wed, Jun 22, 2011 at 8:19 AM, mikedunn
> >> wrote:
> >> >
> >> >> **
> >> >> Varun,
> >> >>
> >> >>
> >> >> On 6/22/2011 9:55 AM, Jeff Brower wrote:
> >> >>
> >> >>
> >> >>
> >> >> Varun-
> >> >>
> >> >> > I am trying to do a Peripheral Device Transfer ( a PDT write by
> >> >> programming
> >> >> > the EDMA and EMIFA registers ) from a FIFO on a Virtex-5 FPGA to a
> >> >> DSK6416
> >> >> > SDRAM.
> >> >> >
> >> >> > My question is, when I look at the EMIF out clock ( ECLKOUT) on the
> >> scope
> >> >> it
> >> >> > DOES NOT look like a square wave but rather like a sinusoidal wave
> >> with a
> >> >> > frequency of 125 MHz and amplitude is 1.6 V.
> >> >> >
> >> >> > Isn't ECLKOUT supposed to look like a square wave. I also grounded
> pin
> >> 75
> >> >> of
> >> >> > J3 in the Peripheral Expansion Connector to GND.
> >> >>
> >> >> How good is your scope? Are you using "active probes"
> (high-impedance,
> >> very
> >> >> low capacitance) ? If not, the mere act
> >> >> of touching your signal with passive probes could make it look as you
> >> >> describe. Suggest to Google "Heisenberg
> >> >> Uncertainty Principle" :-) While 125 MHz is not exactly quantum
> >> mechanics,
> >> >> I expect it's still substantially faster
> >> >> than what you dealt with in your EE lab classes.
> >> >>
> >> >>
> >> >> If your scope and probes are good to display a 125 Mhz square wave,
> you
> >> may
> >> >> have too much capacitance on that signal line.
> >> >> Are you using a wire/cable DCard bus?? If so, how long is it??
> >> >> Or is your FPGA plugged directly into the DCard connector??
> >> >>
> >> >> mikedunn
> >> >>
> >> >>
> >> >> -Jeff
> >> >>
> >> >>
> >> >>
> >> >>
> >> >
> >> >
> >> > --
> >> > Varun
> >> >
> >>
> >>
> >
> >
> > --
> > Varun
> >
--
Varun
with the one unpopulated (for each CLKMODE ).
So, if I bypass those two and make them '00', does that make ECLKIN CLKOUT4 which is eventually ECLKOUT (the EMIF out clock) ??
Thanks,
I also noticed that this is going to reduce the CPU clock speed from 1 GHz
to 100 MHz.
On Wed, Jun 22, 2011 at 3:07 PM, Jeff Brower wrote:
> Varun-
>
> > On the DSK 6416T, the minimum I can reduce the EMIF frequency is to 100
> MHz.
> > by changing the configuration switches on the DSK6416.
> >
> > I am not sure how to connect an external clock to the EMIF's ECLKIN. The
> > EMIF connector does not have an ECLKIN pin on it.
>
> With C64x, you can configure ECLKIN to be CLKOUT4 or CLKOUT6 (CPU clock /4
> and /6). You should be able to adjust CPU
> frequency to be low, for example temporarily mod the CLKMODEn pull-up (or
> pull-down) Rs on the DSK board. Maybe the
> easiest thing is just to temporarily put a jumper wire on both of those to
> ground, bypassing the Rs... as I recall, a
> value of 00 = bypass (no PLL multiplier).
>
> -Jeff
>
> > On Wed, Jun 22, 2011 at 12:47 PM, Jeff Brower > >wrote:
> >
> >> Varun-
> >>
> >> > I am using a Tektronix TAP 1500 (1.5 GHz Active Probe and less than
> 1pF
> >> > input capacitance).
> >> >
> >> > I am using a Tektronix DPO 7254 2.5GHz oscilloscope.
> >>
> >> Scope and probes sound fine. Can you slow down the clock? If a 25 MHz
> >> clock looks Ok, then you might suspect
> >> excessive line length or other sources of loading, as Mike suggested.
> >>
> >> -Jeff
> >>
> >> > On Wed, Jun 22, 2011 at 8:19 AM, mikedunn
> >> wrote:
> >> >
> >> >> **
> >> >> Varun,
> >> >>
> >> >>
> >> >> On 6/22/2011 9:55 AM, Jeff Brower wrote:
> >> >>
> >> >>
> >> >>
> >> >> Varun-
> >> >>
> >> >> > I am trying to do a Peripheral Device Transfer ( a PDT write by
> >> >> programming
> >> >> > the EDMA and EMIFA registers ) from a FIFO on a Virtex-5 FPGA to a
> >> >> DSK6416
> >> >> > SDRAM.
> >> >> >
> >> >> > My question is, when I look at the EMIF out clock ( ECLKOUT) on the
> >> scope
> >> >> it
> >> >> > DOES NOT look like a square wave but rather like a sinusoidal wave
> >> with a
> >> >> > frequency of 125 MHz and amplitude is 1.6 V.
> >> >> >
> >> >> > Isn't ECLKOUT supposed to look like a square wave. I also grounded
> pin
> >> 75
> >> >> of
> >> >> > J3 in the Peripheral Expansion Connector to GND.
> >> >>
> >> >> How good is your scope? Are you using "active probes"
> (high-impedance,
> >> very
> >> >> low capacitance) ? If not, the mere act
> >> >> of touching your signal with passive probes could make it look as you
> >> >> describe. Suggest to Google "Heisenberg
> >> >> Uncertainty Principle" :-) While 125 MHz is not exactly quantum
> >> mechanics,
> >> >> I expect it's still substantially faster
> >> >> than what you dealt with in your EE lab classes.
> >> >>
> >> >>
> >> >> If your scope and probes are good to display a 125 Mhz square wave,
> you
> >> may
> >> >> have too much capacitance on that signal line.
> >> >> Are you using a wire/cable DCard bus?? If so, how long is it??
> >> >> Or is your FPGA plugged directly into the DCard connector??
> >> >>
> >> >> mikedunn
> >> >>
> >> >>
> >> >> -Jeff
> >> >>
> >> >>
> >> >>
> >> >>
> >> >
> >> >
> >> > --
> >> > Varun
> >> >
> >>
> >>
> >
> >
> > --
> > Varun
> >
--
Varun
Reply by ●June 23, 20112011-06-23
Hi Jeff,
On the DSK 6416T, the minimum I can reduce the EMIF frequency is to 100 MHz.
by changing the configuration switches on the DSK6416.
I am not sure how to connect an external clock to the EMIF's ECLKIN. The
EMIF connector does not have an ECLKIN pin on it.
Thanks,
On Wed, Jun 22, 2011 at 12:47 PM, Jeff Brower wrote:
> Varun-
>
> > I am using a Tektronix TAP 1500 (1.5 GHz Active Probe and less than 1pF
> > input capacitance).
> >
> > I am using a Tektronix DPO 7254 2.5GHz oscilloscope.
>
> Scope and probes sound fine. Can you slow down the clock? If a 25 MHz
> clock looks Ok, then you might suspect
> excessive line length or other sources of loading, as Mike suggested.
>
> -Jeff
>
> > On Wed, Jun 22, 2011 at 8:19 AM, mikedunn
> wrote:
> >
> >> **
> >> Varun,
> >>
> >>
> >> On 6/22/2011 9:55 AM, Jeff Brower wrote:
> >>
> >>
> >>
> >> Varun-
> >>
> >> > I am trying to do a Peripheral Device Transfer ( a PDT write by
> >> programming
> >> > the EDMA and EMIFA registers ) from a FIFO on a Virtex-5 FPGA to a
> >> DSK6416
> >> > SDRAM.
> >> >
> >> > My question is, when I look at the EMIF out clock ( ECLKOUT) on the
> scope
> >> it
> >> > DOES NOT look like a square wave but rather like a sinusoidal wave
> with a
> >> > frequency of 125 MHz and amplitude is 1.6 V.
> >> >
> >> > Isn't ECLKOUT supposed to look like a square wave. I also grounded pin
> 75
> >> of
> >> > J3 in the Peripheral Expansion Connector to GND.
> >>
> >> How good is your scope? Are you using "active probes" (high-impedance,
> very
> >> low capacitance) ? If not, the mere act
> >> of touching your signal with passive probes could make it look as you
> >> describe. Suggest to Google "Heisenberg
> >> Uncertainty Principle" :-) While 125 MHz is not exactly quantum
> mechanics,
> >> I expect it's still substantially faster
> >> than what you dealt with in your EE lab classes.
> >>
> >>
> >> If your scope and probes are good to display a 125 Mhz square wave, you
> may
> >> have too much capacitance on that signal line.
> >> Are you using a wire/cable DCard bus?? If so, how long is it??
> >> Or is your FPGA plugged directly into the DCard connector??
> >>
> >> mikedunn
> >>
> >>
> >> -Jeff
> >>
> >>
> >>
> >>
> >
> >
> > --
> > Varun
> >
--
Varun
On the DSK 6416T, the minimum I can reduce the EMIF frequency is to 100 MHz.
by changing the configuration switches on the DSK6416.
I am not sure how to connect an external clock to the EMIF's ECLKIN. The
EMIF connector does not have an ECLKIN pin on it.
Thanks,
On Wed, Jun 22, 2011 at 12:47 PM, Jeff Brower wrote:
> Varun-
>
> > I am using a Tektronix TAP 1500 (1.5 GHz Active Probe and less than 1pF
> > input capacitance).
> >
> > I am using a Tektronix DPO 7254 2.5GHz oscilloscope.
>
> Scope and probes sound fine. Can you slow down the clock? If a 25 MHz
> clock looks Ok, then you might suspect
> excessive line length or other sources of loading, as Mike suggested.
>
> -Jeff
>
> > On Wed, Jun 22, 2011 at 8:19 AM, mikedunn
> wrote:
> >
> >> **
> >> Varun,
> >>
> >>
> >> On 6/22/2011 9:55 AM, Jeff Brower wrote:
> >>
> >>
> >>
> >> Varun-
> >>
> >> > I am trying to do a Peripheral Device Transfer ( a PDT write by
> >> programming
> >> > the EDMA and EMIFA registers ) from a FIFO on a Virtex-5 FPGA to a
> >> DSK6416
> >> > SDRAM.
> >> >
> >> > My question is, when I look at the EMIF out clock ( ECLKOUT) on the
> scope
> >> it
> >> > DOES NOT look like a square wave but rather like a sinusoidal wave
> with a
> >> > frequency of 125 MHz and amplitude is 1.6 V.
> >> >
> >> > Isn't ECLKOUT supposed to look like a square wave. I also grounded pin
> 75
> >> of
> >> > J3 in the Peripheral Expansion Connector to GND.
> >>
> >> How good is your scope? Are you using "active probes" (high-impedance,
> very
> >> low capacitance) ? If not, the mere act
> >> of touching your signal with passive probes could make it look as you
> >> describe. Suggest to Google "Heisenberg
> >> Uncertainty Principle" :-) While 125 MHz is not exactly quantum
> mechanics,
> >> I expect it's still substantially faster
> >> than what you dealt with in your EE lab classes.
> >>
> >>
> >> If your scope and probes are good to display a 125 Mhz square wave, you
> may
> >> have too much capacitance on that signal line.
> >> Are you using a wire/cable DCard bus?? If so, how long is it??
> >> Or is your FPGA plugged directly into the DCard connector??
> >>
> >> mikedunn
> >>
> >>
> >> -Jeff
> >>
> >>
> >>
> >>
> >
> >
> > --
> > Varun
> >
--
Varun
Reply by ●June 28, 20112011-06-28
Varun-
> Thanks Jeff. I found those R's. They are in a resistor
> divider combination
> with the one unpopulated (for each CLKMODE ).
>
> So, if I bypass those two and make them '00', does that
> make ECLKIN CLKOUT4 which is eventually ECLKOUT (the EMIF out
> clock) ??
If you set CLKMODE to bypass, then the CPU speed will be the external oscillator rate (not sure what that is on the
DSK 6416). As for ECLKIN, you might read pg. 10 in this doc:
http://focus.ti.com/lit/an/spra430a/spra430a.pdf
which indicates that EMIF can be configured via pull-up/down Rs to use CLKOUT4 or CLKOUT6 as ECLKIN. I'm not sure
where are these Rs on the DSK 6416.
> I also noticed that this is going to reduce the CPU clock speed from 1 GHz
> to 100 MHz.
That's Ok for testing purposes.
-Jeff
> On Wed, Jun 22, 2011 at 3:07 PM, Jeff Brower wrote:
>
>> Varun-
>>
>> > On the DSK 6416T, the minimum I can reduce the EMIF frequency is to 100
>> MHz.
>> > by changing the configuration switches on the DSK6416.
>> >
>> > I am not sure how to connect an external clock to the EMIF's ECLKIN. The
>> > EMIF connector does not have an ECLKIN pin on it.
>>
>> With C64x, you can configure ECLKIN to be CLKOUT4 or CLKOUT6 (CPU clock /4
>> and /6). You should be able to adjust CPU
>> frequency to be low, for example temporarily mod the CLKMODEn pull-up (or
>> pull-down) Rs on the DSK board. Maybe the
>> easiest thing is just to temporarily put a jumper wire on both of those to
>> ground, bypassing the Rs... as I recall, a
>> value of 00 = bypass (no PLL multiplier).
>>
>> -Jeff
>>
>> > On Wed, Jun 22, 2011 at 12:47 PM, Jeff Brower >> >wrote:
>> >
>> >> Varun-
>> >>
>> >> > I am using a Tektronix TAP 1500 (1.5 GHz Active Probe and less than
>> 1pF
>> >> > input capacitance).
>> >> >
>> >> > I am using a Tektronix DPO 7254 2.5GHz oscilloscope.
>> >>
>> >> Scope and probes sound fine. Can you slow down the clock? If a 25 MHz
>> >> clock looks Ok, then you might suspect
>> >> excessive line length or other sources of loading, as Mike suggested.
>> >>
>> >> -Jeff
>> >>
>> >> > On Wed, Jun 22, 2011 at 8:19 AM, mikedunn
>> >> wrote:
>> >> >
>> >> >> **
>> >> >> Varun,
>> >> >>
>> >> >>
>> >> >> On 6/22/2011 9:55 AM, Jeff Brower wrote:
>> >> >>
>> >> >>
>> >> >>
>> >> >> Varun-
>> >> >>
>> >> >> > I am trying to do a Peripheral Device Transfer ( a PDT write by
>> >> >> programming
>> >> >> > the EDMA and EMIFA registers ) from a FIFO on a Virtex-5 FPGA to a
>> >> >> DSK6416
>> >> >> > SDRAM.
>> >> >> >
>> >> >> > My question is, when I look at the EMIF out clock ( ECLKOUT) on the
>> >> scope
>> >> >> it
>> >> >> > DOES NOT look like a square wave but rather like a sinusoidal wave
>> >> with a
>> >> >> > frequency of 125 MHz and amplitude is 1.6 V.
>> >> >> >
>> >> >> > Isn't ECLKOUT supposed to look like a square wave. I also grounded
>> pin
>> >> 75
>> >> >> of
>> >> >> > J3 in the Peripheral Expansion Connector to GND.
>> >> >>
>> >> >> How good is your scope? Are you using "active probes"
>> (high-impedance,
>> >> very
>> >> >> low capacitance) ? If not, the mere act
>> >> >> of touching your signal with passive probes could make it look as you
>> >> >> describe. Suggest to Google "Heisenberg
>> >> >> Uncertainty Principle" :-) While 125 MHz is not exactly quantum
>> >> mechanics,
>> >> >> I expect it's still substantially faster
>> >> >> than what you dealt with in your EE lab classes.
>> >> >>
>> >> >>
>> >> >> If your scope and probes are good to display a 125 Mhz square wave,
>> you
>> >> may
>> >> >> have too much capacitance on that signal line.
>> >> >> Are you using a wire/cable DCard bus?? If so, how long is it??
>> >> >> Or is your FPGA plugged directly into the DCard connector??
>> >> >>
>> >> >> mikedunn
>> >> >>
>> >> >>
>> >> >> -Jeff
_____________________________________
> Thanks Jeff. I found those R's. They are in a resistor
> divider combination
> with the one unpopulated (for each CLKMODE ).
>
> So, if I bypass those two and make them '00', does that
> make ECLKIN CLKOUT4 which is eventually ECLKOUT (the EMIF out
> clock) ??
If you set CLKMODE to bypass, then the CPU speed will be the external oscillator rate (not sure what that is on the
DSK 6416). As for ECLKIN, you might read pg. 10 in this doc:
http://focus.ti.com/lit/an/spra430a/spra430a.pdf
which indicates that EMIF can be configured via pull-up/down Rs to use CLKOUT4 or CLKOUT6 as ECLKIN. I'm not sure
where are these Rs on the DSK 6416.
> I also noticed that this is going to reduce the CPU clock speed from 1 GHz
> to 100 MHz.
That's Ok for testing purposes.
-Jeff
> On Wed, Jun 22, 2011 at 3:07 PM, Jeff Brower wrote:
>
>> Varun-
>>
>> > On the DSK 6416T, the minimum I can reduce the EMIF frequency is to 100
>> MHz.
>> > by changing the configuration switches on the DSK6416.
>> >
>> > I am not sure how to connect an external clock to the EMIF's ECLKIN. The
>> > EMIF connector does not have an ECLKIN pin on it.
>>
>> With C64x, you can configure ECLKIN to be CLKOUT4 or CLKOUT6 (CPU clock /4
>> and /6). You should be able to adjust CPU
>> frequency to be low, for example temporarily mod the CLKMODEn pull-up (or
>> pull-down) Rs on the DSK board. Maybe the
>> easiest thing is just to temporarily put a jumper wire on both of those to
>> ground, bypassing the Rs... as I recall, a
>> value of 00 = bypass (no PLL multiplier).
>>
>> -Jeff
>>
>> > On Wed, Jun 22, 2011 at 12:47 PM, Jeff Brower >> >wrote:
>> >
>> >> Varun-
>> >>
>> >> > I am using a Tektronix TAP 1500 (1.5 GHz Active Probe and less than
>> 1pF
>> >> > input capacitance).
>> >> >
>> >> > I am using a Tektronix DPO 7254 2.5GHz oscilloscope.
>> >>
>> >> Scope and probes sound fine. Can you slow down the clock? If a 25 MHz
>> >> clock looks Ok, then you might suspect
>> >> excessive line length or other sources of loading, as Mike suggested.
>> >>
>> >> -Jeff
>> >>
>> >> > On Wed, Jun 22, 2011 at 8:19 AM, mikedunn
>> >> wrote:
>> >> >
>> >> >> **
>> >> >> Varun,
>> >> >>
>> >> >>
>> >> >> On 6/22/2011 9:55 AM, Jeff Brower wrote:
>> >> >>
>> >> >>
>> >> >>
>> >> >> Varun-
>> >> >>
>> >> >> > I am trying to do a Peripheral Device Transfer ( a PDT write by
>> >> >> programming
>> >> >> > the EDMA and EMIFA registers ) from a FIFO on a Virtex-5 FPGA to a
>> >> >> DSK6416
>> >> >> > SDRAM.
>> >> >> >
>> >> >> > My question is, when I look at the EMIF out clock ( ECLKOUT) on the
>> >> scope
>> >> >> it
>> >> >> > DOES NOT look like a square wave but rather like a sinusoidal wave
>> >> with a
>> >> >> > frequency of 125 MHz and amplitude is 1.6 V.
>> >> >> >
>> >> >> > Isn't ECLKOUT supposed to look like a square wave. I also grounded
>> pin
>> >> 75
>> >> >> of
>> >> >> > J3 in the Peripheral Expansion Connector to GND.
>> >> >>
>> >> >> How good is your scope? Are you using "active probes"
>> (high-impedance,
>> >> very
>> >> >> low capacitance) ? If not, the mere act
>> >> >> of touching your signal with passive probes could make it look as you
>> >> >> describe. Suggest to Google "Heisenberg
>> >> >> Uncertainty Principle" :-) While 125 MHz is not exactly quantum
>> >> mechanics,
>> >> >> I expect it's still substantially faster
>> >> >> than what you dealt with in your EE lab classes.
>> >> >>
>> >> >>
>> >> >> If your scope and probes are good to display a 125 Mhz square wave,
>> you
>> >> may
>> >> >> have too much capacitance on that signal line.
>> >> >> Are you using a wire/cable DCard bus?? If so, how long is it??
>> >> >> Or is your FPGA plugged directly into the DCard connector??
>> >> >>
>> >> >> mikedunn
>> >> >>
>> >> >>
>> >> >> -Jeff
_____________________________________
