Hello Everyone,
I am trying to do a *Peripheral Device Transfer (PDT)* from an FPGA *(FIFO
on a Virtex-5)* to a *DSK6416*. The data is 8-bit and fifo depth is 32.
The FULL flag of the FIFO will trigger a PDT (an EDMA event). The FULL flag
of the FIFO is connected to *EXT_INT7* which will trigger the EDMA
event *EDMA_EVT_EXTINT7
( channel # 7 of C6416T ).*
*
*
The FIFO worked perfectly in simulation as well as on the Virtex-5. It runs
on *ECLKOUT*.* ( I checked ECLKOUT by running a counter on the FPGA ).*
Connections between DSK and FPGA were setup according to *XAPP753*.
(I've
attached the screenshot of the setup.)
Initially I tested to see whether the FULL flag is interrupting the CPU or
not and it did.
The problem is when I programmed the EDMA for channel 7, the FULL flag did
not trigger the event. ( It did not *set* the *EDMA EVENT SET register -
ESR w.r.t channel 7 ).*
So I tried to set the ESR (to trigger the event) by using *EDMA_setChannel(
handle) or EDMA_RSET(ESRL,value). *This neither set the bit in the ESR nor
did it change the corresponding bit in the *Event Register (ERL).* I tried
another channel as well but that didn't work too. Does anyone have any
idea
what could be the reason ?
I have attached my code and a screenshot of the FPGA-DSP connection.
Even after setting up the *CE space 0* as* 8-bit* wide SDRAM, BE signal
wasn't driven *LOW.* Any suggestions would be extremely helpful. Thanks
in
advance.
Regards,
--
Varun
