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C6711: FFT without disabling interrupts

Started by Unknown January 22, 2003

I think that Pete is certainly correct when he says you don't have control over
interrupts in TI's hand optimized asm functions (ie FFTs).

That said, it is often useful to back up a little and look at the big picture.
Before doing an FFT we need to collect the samples/data from somewhere -
assuming a real-time embedded system. The C6x1x has EDMA channels on chip that
support the collection of samples in the background. In many instances this
allows the DSP to process blocks of samples after the background collection has
completed. Ping-ponging linked EDMA transfers allows continuous collection
without dropouts.

Of course I do understand the issue that if there is an external event that you
HAVE TO "intelligently" (not just EDMA transfer) respond in less than x usec,
then you are sunk. Time to choose a different DSP !

Andrew E.

At 06:25 PM 1/24/2003 +0000, pete wrote:
>Hello is this thing on?
>
>I have to agree with everything that Jeff says, Real time issues are
>vital -- something that TI don't care about when making benchmarks.
>
>I still think you are ignoring the fact that you have NO control over
>what a function written in hand coded assembler does. It is already
>compiled and has interrupts OFF -- no choices.
>
>This is why the TI functions are not useful in real life.
>
>Pete Warnes
>Technical director
>HUNT ENGINEERING (U.K.) Ltd
>email
>URL http://www.hunteng.co.uk or http://www.hunt-dsp.com
>phone +44 (0)1278 760188
>direct +44 (0)1278 760966
>GSM +44 (0)7711 190099
>Fax +44 (0)1278 760199
>
>> -----Original Message-----
>> From: Jeff Brower [mailto:]
>> Sent: Friday, January 24, 2003 5:49 PM
>> To: Jean-Michel MERCIER
>> Cc:
>> Subject: Re: [c6x] C6711: FFT without disabling interrupts
>>
>>
>> Jean-Michel MERCIER-
>>
>> > It is not a problem of loosing sample interrupts.
>>
>> It is if you leave interrupts disabled too long -- that's my
>> main point, and I think
>> it's important that anyone learning DSP knows that if you
>> miss analog input samples
>> by paying too much attention to optimizing code, the game is over.
>>
>> Maintaining real-time operation with analog or digital I/O at
>> the same time as code
>> optimization, piplelining, linear assembly, etc. is a
>> real-world trade-off that must
>> be dealt with in most systems.
>>
>> Jeff Brower
>> DSP sw/hw engineer
>> Signalogic
>>
>>
>> > It is a problem that if you get an interrupt
>> > while in optimzed pipelined code, you will
>> > break the pipeline context whatever you
>> > will try to save in the ISR.
>> >
>> > If you have a code such as :
>> >
>> > LDW xxx, A1
>> > some instruction
>> > some instruction
>> > some instruction
>> > some instruction
>> > ADD A1, A2
>> >
>> > This code MUST be interrupt-protected.
>> > If any interrupt come between the LDW and the ADD,
>> > the data that have started its journey in the
>> > pipeline will be lost because the ISR will
>> > not be able to save the content of the pipeline,
>> > but only what have already reached register content.
>> >
>> > That is why CCS compiler introduce som many NOPs
>> > This code should be written as :
>> >
>> > LDW xxx, A1
>> > NOP 4
>> > ADD A1, A2
>> >
>> > because "NOP n" is not interruptable !
>> >
>> > Best regards,
>> >
>> > Jean-Michel MERCIER
>> >
>> > --
>> > dsp & imaging - www.ateme.com
>> > ATEME - 26 Burospace - 91573 BIEVRES
>> > Tel : +33 (0)1 69 35 89 73 (direct)
>> > Fax : +33 (0)1 60 19 13 95
>>
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