BAS-
I know I mentioned this already... but... multicore.
One core could be doing decimation, another one your processing.
Check out C66x series. Cores share substantial onchip memory area. And all
cores are floating-point.
-Jeff
>> Date: Thu, 3 Jan 2013 05:15:36 -0800 (PST)
>> From: B S
>> Cc: Richard Williams
>> Subject: Re: [c6x] Re: SWI vs. TSK
>>
>> I could have taken your suggestion if I had an option to use McASP or
slower
>> ADC. I have to use OMAP-L138 EVM with 20 MSPS ADC. One application of my
>> project is dealing with 1 MHz signal which make sense to use that ADC. I
have
>> to deal with 50 Hz signal using the same device. Therefore, digital
filtering
>> + decimation is the only solution i see right now.
>
> Let me assume Fs is 2MHz to get a 1MHz band. Then, if CPU rate is 300MHz,
you
> get no more than 150 clocks to process a single sample in your 1MHz
digitized
> signal.
>
> Then, you may have to downsample it to 1KHz band, then you just need to
take
> one sample out of every 1,000, and filter out aliasing frequencies above
1KHz,
> that is between 1KHz and 2MHz. I guess this is going to be a long filter.
>
> I think you will have to use more CPUs and also split the analog input
signal
> into 2 channels, one sampled at a high rate, the other at a slower rate.
This
> would remove downsampling and antialiasing filter out from your system.
>
>> BTW, do you have any idea how could I implement decimation filter
>> (Butterworth or Chebyshev) in C ?
>
> I have seen a couple of windows programs on the net that design a digital
> filter. They calculate coefficients for either FIR or IIR filter type,
> whichever suits better for you system.
>
> Rgds,
> Andrew
>
>> From: Andrew Nesterov
>> To: c...
>> Sent: Wednesday, January 2, 2013 10:56 PM
>> Subject: [c6x] Re: SWI vs. TSK
>> Hi B.S.,
>>
>>> ---------- Original Message -----------
>>> From: B S
>>>>
>>>> I want to capture 50 Hz signal with sampling frequency not more than 2
>>>> kHz. I am using OMAP-L138 EVM with has ADS901 attached with it. It has
>>>> sampling rate 20 MSPS, I can't get less than 212.60 kHz sampling
rate
>>>> because it uses programmable PLL (CDCE913) to set the clock. I will
>>>> have to do downsampling which I haven't figured out yet.
>>
>> Most probably I have missed some bits of important information, but from
>> what I can see now, why wouldn't one would use a slow audio type of
an
>> ADC device and McASP to read samples digitized at exactly Fs = 2,000Hz?
>>
>> I think there are plenty of such devices out there on the market and
>> they must be much cheaper to purchase, rather than more expensive
>> speedy device of 20,000,000Hz sampling rate...
>>
>> Using a right device one wouldn't have to employ a numerically
expensive
>> downsampling procedure that has to apply a digital filter to remove
>> 19,999 samples and free the CPU to perform other important tasks...
>>
>> Have I rally missed something?
>>
>> Rgds,
>>
>> Andrew
_____________________________________
SWI vs. TSK
Started by ●November 25, 2012
Reply by ●January 4, 20132013-01-04
Reply by ●January 17, 20132013-01-17
Hi,
Thanks for all your help. Unfortunately, I can't change the processor at this point so sticking with it is the only option.
However, I appreciate your help with the following query.
If sampling at 200kHz then capturing 1024 point data takes (1/200k * 1024 = 5.12 mSec). This way I know i need atleast 4 buffer of size 1024 to capture a 50 Hz cycle. In my case it's DMA which transfers data to CPU and it always takes 17 CPU cycle. How would I know in this case that how much samples i need to get a 50 Hz cycle ?
Thanks.
________________________________
From: Jeff Brower
To: B S
Cc: c...
Sent: Friday, January 4, 2013 6:32 AM
Subject: Re: [c6x] Re: SWI vs. TSK
BAS-
I know I mentioned this already... but... multicore.
One core could be doing decimation, another one your processing.
Check out C66x series. Cores share substantial onchip memory area. And all cores are floating-point.
-Jeff
>> Date: Thu, 3 Jan 2013 05:15:36 -0800 (PST)
>> From: B S
> Cc: Richard Williams
>> Subject: Re: [c6x] Re: SWI vs. TSK
>>
>> I could have taken your suggestion if I had an option to use McASP or slower
>> ADC. I have to use OMAP-L138 EVM with 20 MSPS ADC. One application of my
>> project is dealing with 1 MHz signal which make sense to use that ADC. I have
>> to deal with 50 Hz signal using the same device. Therefore, digital filtering
>> + decimation is the only solution i see right now.
>
> Let me assume Fs is 2MHz to get a 1MHz band. Then, if CPU rate is 300MHz, you
> get no more than 150 clocks to process a single sample in your 1MHz digitized
> signal.
>
> Then, you may have to downsample it to 1KHz band, then you just need to take
> one sample out of every 1,000, and filter out aliasing frequencies above 1KHz,
> that is between 1KHz and 2MHz. I guess this is going to be a long filter.
>
> I think you will have to use more CPUs and also split the analog input signal
> into 2 channels, one sampled at a high rate, the other at a slower rate. This
> would remove downsampling and antialiasing filter out from your system.
>
>> BTW, do you have any idea how could I implement decimation filter
>> (Butterworth or Chebyshev) in C ?
>
> I have seen a couple of windows programs on the net that design a digital
> filter. They calculate coefficients for either FIR or IIR filter type,
> whichever suits better for you system.
>
> Rgds,
> Andrew
>
>> From: Andrew Nesterov
> To: c...
>> Sent: Wednesday, January 2, 2013 10:56 PM
>> Subject: [c6x] Re: SWI vs. TSK
>> Hi B.S.,
>>
>>> ---------- Original Message -----------
>>> From: B S
>>>
>>>> I want to capture 50 Hz signal with sampling frequency not more than 2
>>>> kHz. I am using OMAP-L138 EVM with has ADS901 attached with it. It has
>>>> sampling rate 20 MSPS, I can't get less than 212.60 kHz sampling rate
>>>> because it uses programmable PLL (CDCE913) to set the clock. I will
>>>> have to do downsampling which I haven't figured out yet.
>>
>> Most probably I have missed some bits of important information, but from
>> what I can see now, why wouldn't one would use a slow audio type of an
>> ADC device and McASP to read samples digitized at exactly Fs = 2,000Hz?
>>
>> I think there are plenty of such devices out there on the market and
>> they must be much cheaper to purchase, rather than more expensive
>> speedy device of 20,000,000Hz sampling rate...
>>
>> Using a right device one wouldn't have to employ a numerically expensive
>> downsampling procedure that has to apply a digital filter to remove
>> 19,999 samples and free the CPU to perform other important tasks...
>>
>> Have I rally missed something?
>>
>> Rgds,
>>
>> Andrew
Thanks for all your help. Unfortunately, I can't change the processor at this point so sticking with it is the only option.
However, I appreciate your help with the following query.
If sampling at 200kHz then capturing 1024 point data takes (1/200k * 1024 = 5.12 mSec). This way I know i need atleast 4 buffer of size 1024 to capture a 50 Hz cycle. In my case it's DMA which transfers data to CPU and it always takes 17 CPU cycle. How would I know in this case that how much samples i need to get a 50 Hz cycle ?
Thanks.
________________________________
From: Jeff Brower
To: B S
Cc: c...
Sent: Friday, January 4, 2013 6:32 AM
Subject: Re: [c6x] Re: SWI vs. TSK
BAS-
I know I mentioned this already... but... multicore.
One core could be doing decimation, another one your processing.
Check out C66x series. Cores share substantial onchip memory area. And all cores are floating-point.
-Jeff
>> Date: Thu, 3 Jan 2013 05:15:36 -0800 (PST)
>> From: B S
> Cc: Richard Williams
>> Subject: Re: [c6x] Re: SWI vs. TSK
>>
>> I could have taken your suggestion if I had an option to use McASP or slower
>> ADC. I have to use OMAP-L138 EVM with 20 MSPS ADC. One application of my
>> project is dealing with 1 MHz signal which make sense to use that ADC. I have
>> to deal with 50 Hz signal using the same device. Therefore, digital filtering
>> + decimation is the only solution i see right now.
>
> Let me assume Fs is 2MHz to get a 1MHz band. Then, if CPU rate is 300MHz, you
> get no more than 150 clocks to process a single sample in your 1MHz digitized
> signal.
>
> Then, you may have to downsample it to 1KHz band, then you just need to take
> one sample out of every 1,000, and filter out aliasing frequencies above 1KHz,
> that is between 1KHz and 2MHz. I guess this is going to be a long filter.
>
> I think you will have to use more CPUs and also split the analog input signal
> into 2 channels, one sampled at a high rate, the other at a slower rate. This
> would remove downsampling and antialiasing filter out from your system.
>
>> BTW, do you have any idea how could I implement decimation filter
>> (Butterworth or Chebyshev) in C ?
>
> I have seen a couple of windows programs on the net that design a digital
> filter. They calculate coefficients for either FIR or IIR filter type,
> whichever suits better for you system.
>
> Rgds,
> Andrew
>
>> From: Andrew Nesterov
> To: c...
>> Sent: Wednesday, January 2, 2013 10:56 PM
>> Subject: [c6x] Re: SWI vs. TSK
>> Hi B.S.,
>>
>>> ---------- Original Message -----------
>>> From: B S
>>>
>>>> I want to capture 50 Hz signal with sampling frequency not more than 2
>>>> kHz. I am using OMAP-L138 EVM with has ADS901 attached with it. It has
>>>> sampling rate 20 MSPS, I can't get less than 212.60 kHz sampling rate
>>>> because it uses programmable PLL (CDCE913) to set the clock. I will
>>>> have to do downsampling which I haven't figured out yet.
>>
>> Most probably I have missed some bits of important information, but from
>> what I can see now, why wouldn't one would use a slow audio type of an
>> ADC device and McASP to read samples digitized at exactly Fs = 2,000Hz?
>>
>> I think there are plenty of such devices out there on the market and
>> they must be much cheaper to purchase, rather than more expensive
>> speedy device of 20,000,000Hz sampling rate...
>>
>> Using a right device one wouldn't have to employ a numerically expensive
>> downsampling procedure that has to apply a digital filter to remove
>> 19,999 samples and free the CPU to perform other important tasks...
>>
>> Have I rally missed something?
>>
>> Rgds,
>>
>> Andrew
Reply by ●January 17, 20132013-01-17
Hi;
If your objective is to capture the 50 Hz, all you need is (more or less) 0.5 cycle of the 50 Hz to get all the needed information of the 50Hz. Half cycle is defined by two consecutive zero crossings or positive peak followed by a negative peak (or negative followed by positive peak). This will reduce he buffer size needed.
Omar
--- On Wed, 1/9/13, B S wrote:
From: B S
Subject: Re: [c6x] Re: SWI vs. TSK
To: "Jeff Brower"
Cc: "c..."
Date: Wednesday, January 9, 2013, 5:41 AM
Hi,
Thanks for all your help. Unfortunately, I can't change the processor at this point so sticking with it is the only option.
However, I appreciate your help with the following query.
If sampling at 200kHz then capturing 1024 point data takes (1/200k * 1024 = 5.12 mSec). This way I know i need atleast 4 buffer of size 1024 to capture a 50 Hz cycle. In my case it's DMA which transfers data to CPU and it always takes 17 CPU cycle. How would I know in this case that how much samples i need to get a 50 Hz cycle ?
Thanks.
From: Jeff Brower
To: B S
Cc: c...
Sent: Friday, January 4, 2013 6:32 AM
Subject: Re: [c6x] Re: SWI vs. TSK
BAS-
I know I mentioned this already... but... multicore.
One core could be doing decimation, another one your processing.
Check out C66x series. Cores share substantial onchip memory area. And all cores are floating-point.
-Jeff
>> Date: Thu, 3 Jan 2013 05:15:36 -0800 (PST)
>> From: B S
> Cc: Richard Williams
>> Subject: Re: [c6x] Re: SWI vs. TSK
>>
>> I could have taken your suggestion if I had an option to use McASP or slower
>> ADC. I have to use OMAP-L138 EVM with 20 MSPS ADC. One application of my
>> project is dealing with 1 MHz signal which make sense to use that ADC. I have
>> to deal with 50 Hz signal using the same device. Therefore, digital filtering
>> + decimation is the only solution i see right now.
>
> Let me assume Fs is 2MHz to get a 1MHz band. Then, if CPU rate is 300MHz, you
> get no more than 150 clocks to process a single sample in your 1MHz digitized
> signal.
>
> Then, you may have to downsample it to 1KHz band, then you just need to take
> one sample out of every 1,000, and filter out aliasing frequencies above 1KHz,
> that is between 1KHz and 2MHz. I guess this is going to be a long filter.
>
> I think you will have to use more CPUs and also split the analog input signal
> into 2 channels, one sampled at a high rate, the other at a slower rate. This
> would remove downsampling and antialiasing filter out from your system.
>
>> BTW, do you have any idea how could I implement decimation filter
>> (Butterworth or Chebyshev) in C ?
>
> I have seen a couple of windows programs on the net that design a digital
> filter. They calculate coefficients for either FIR or IIR filter type,
> whichever suits better for you system.
>
> Rgds,
> Andrew
>
>> From: Andrew Nesterov
> To: c...
>> Sent: Wednesday, January 2, 2013 10:56 PM
>> Subject: [c6x] Re: SWI vs. TSK
>>
>>
>> Hi B.S.,
>>
>>> ---------- Original Message -----------
>>> From: B S
>>>
>>>> I want to capture 50 Hz signal with sampling frequency not more than 2
>>>> kHz. I am using OMAP-L138 EVM with has ADS901 attached with it. It has
>>>> sampling rate 20 MSPS, I can't get less than 212.60 kHz sampling rate
>>>> because it uses programmable PLL (CDCE913) to set the clock. I will
>>>> have to do downsampling which I haven't figured out yet.
>>
>> Most probably I have missed some bits of important information, but from
>> what I can see now, why wouldn't one would use a slow audio type of an
>> ADC device and McASP to read samples digitized at exactly Fs = 2,000Hz?
>>
>> I think there are plenty of such devices out there on the market and
>> they must be much cheaper to purchase, rather than more expensive
>> speedy device of 20,000,000Hz sampling rate...
>>
>> Using a right device one wouldn't have to employ a numerically expensive
>> downsampling procedure that has to apply a digital filter to remove
>> 19,999 samples and free the CPU to perform other important tasks...
>>
>> Have I rally missed something?
>>
>> Rgds,
>>
>> Andrew
If your objective is to capture the 50 Hz, all you need is (more or less) 0.5 cycle of the 50 Hz to get all the needed information of the 50Hz. Half cycle is defined by two consecutive zero crossings or positive peak followed by a negative peak (or negative followed by positive peak). This will reduce he buffer size needed.
Omar
--- On Wed, 1/9/13, B S wrote:
From: B S
Subject: Re: [c6x] Re: SWI vs. TSK
To: "Jeff Brower"
Cc: "c..."
Date: Wednesday, January 9, 2013, 5:41 AM
Hi,
Thanks for all your help. Unfortunately, I can't change the processor at this point so sticking with it is the only option.
However, I appreciate your help with the following query.
If sampling at 200kHz then capturing 1024 point data takes (1/200k * 1024 = 5.12 mSec). This way I know i need atleast 4 buffer of size 1024 to capture a 50 Hz cycle. In my case it's DMA which transfers data to CPU and it always takes 17 CPU cycle. How would I know in this case that how much samples i need to get a 50 Hz cycle ?
Thanks.
From: Jeff Brower
To: B S
Cc: c...
Sent: Friday, January 4, 2013 6:32 AM
Subject: Re: [c6x] Re: SWI vs. TSK
BAS-
I know I mentioned this already... but... multicore.
One core could be doing decimation, another one your processing.
Check out C66x series. Cores share substantial onchip memory area. And all cores are floating-point.
-Jeff
>> Date: Thu, 3 Jan 2013 05:15:36 -0800 (PST)
>> From: B S
> Cc: Richard Williams
>> Subject: Re: [c6x] Re: SWI vs. TSK
>>
>> I could have taken your suggestion if I had an option to use McASP or slower
>> ADC. I have to use OMAP-L138 EVM with 20 MSPS ADC. One application of my
>> project is dealing with 1 MHz signal which make sense to use that ADC. I have
>> to deal with 50 Hz signal using the same device. Therefore, digital filtering
>> + decimation is the only solution i see right now.
>
> Let me assume Fs is 2MHz to get a 1MHz band. Then, if CPU rate is 300MHz, you
> get no more than 150 clocks to process a single sample in your 1MHz digitized
> signal.
>
> Then, you may have to downsample it to 1KHz band, then you just need to take
> one sample out of every 1,000, and filter out aliasing frequencies above 1KHz,
> that is between 1KHz and 2MHz. I guess this is going to be a long filter.
>
> I think you will have to use more CPUs and also split the analog input signal
> into 2 channels, one sampled at a high rate, the other at a slower rate. This
> would remove downsampling and antialiasing filter out from your system.
>
>> BTW, do you have any idea how could I implement decimation filter
>> (Butterworth or Chebyshev) in C ?
>
> I have seen a couple of windows programs on the net that design a digital
> filter. They calculate coefficients for either FIR or IIR filter type,
> whichever suits better for you system.
>
> Rgds,
> Andrew
>
>> From: Andrew Nesterov
> To: c...
>> Sent: Wednesday, January 2, 2013 10:56 PM
>> Subject: [c6x] Re: SWI vs. TSK
>>
>>
>> Hi B.S.,
>>
>>> ---------- Original Message -----------
>>> From: B S
>>>
>>>> I want to capture 50 Hz signal with sampling frequency not more than 2
>>>> kHz. I am using OMAP-L138 EVM with has ADS901 attached with it. It has
>>>> sampling rate 20 MSPS, I can't get less than 212.60 kHz sampling rate
>>>> because it uses programmable PLL (CDCE913) to set the clock. I will
>>>> have to do downsampling which I haven't figured out yet.
>>
>> Most probably I have missed some bits of important information, but from
>> what I can see now, why wouldn't one would use a slow audio type of an
>> ADC device and McASP to read samples digitized at exactly Fs = 2,000Hz?
>>
>> I think there are plenty of such devices out there on the market and
>> they must be much cheaper to purchase, rather than more expensive
>> speedy device of 20,000,000Hz sampling rate...
>>
>> Using a right device one wouldn't have to employ a numerically expensive
>> downsampling procedure that has to apply a digital filter to remove
>> 19,999 samples and free the CPU to perform other important tasks...
>>
>> Have I rally missed something?
>>
>> Rgds,
>>
>> Andrew
Reply by ●January 18, 20132013-01-18
BSA-
> Thanks for all your help. Unfortunately, I can't change
> the processor at this point so sticking with it is the only
> option.
>
> However, I appreciate your help with the following query.
>
> If sampling at 200kHz then capturing 1024 point data takes
> (1/200k * 1024 = 5.12 mSec). This way I know i need atleast
> 4 buffer of size 1024 to capture a 50 Hz cycle. In my case
> it's DMA which transfers data to CPU and it always takes 17
> CPU cycle. How would I know in this case that how much
> samples i need to get a 50 Hz cycle ?
4 samples.
-Jeff
> ________________________________
> From: Jeff Brower
> To: B S
> Cc: c...
> Sent: Friday, January 4, 2013 6:32 AM
> Subject: Re: [c6x] Re: SWI vs. TSK
>
> BAS-
>
> I know I mentioned this already... but... multicore.
>
> One core could be doing decimation, another one your processing.
>
> Check out C66x series. Cores share substantial onchip memory area. And all cores are floating-point.
>
> -Jeff
>
>>> Date: Thu, 3 Jan 2013 05:15:36 -0800 (PST)
>>> From: B S
>> Cc: Richard Williams
>>> Subject: Re: [c6x] Re: SWI vs. TSK
>>>
>>> I could have taken your suggestion if I had an option to use McASP or slower
>>> ADC. I have to use OMAP-L138 EVM with 20 MSPS ADC. One application of my
>>> project is dealing with 1 MHz signal which make sense to use that ADC. I have
>>> to deal with 50 Hz signal using the same device. Therefore, digital filtering
>>> + decimation is the only solution i see right now.
>>
>> Let me assume Fs is 2MHz to get a 1MHz band. Then, if CPU rate is 300MHz, you
>> get no more than 150 clocks to process a single sample in your 1MHz digitized
>> signal.
>>
>> Then, you may have to downsample it to 1KHz band, then you just need to take
>> one sample out of every 1,000, and filter out aliasing frequencies above 1KHz,
>> that is between 1KHz and 2MHz. I guess this is going to be a long filter.
>>
>> I think you will have to use more CPUs and also split the analog input signal
>> into 2 channels, one sampled at a high rate, the other at a slower rate. This
>> would remove downsampling and antialiasing filter out from your system.
>>
>>> BTW, do you have any idea how could I implement decimation filter
>>> (Butterworth or Chebyshev) in C ?
>>
>> I have seen a couple of windows programs on the net that design a digital
>> filter. They calculate coefficients for either FIR or IIR filter type,
>> whichever suits better for you system.
>>
>> Rgds,
>> Andrew
>>
>>> From: Andrew Nesterov
>> To: c...
>>> Sent: Wednesday, January 2, 2013 10:56 PM
>>> Subject: [c6x] Re: SWI vs. TSK
>>>
>>>
>>> Hi B.S.,
>>>
>>>> ---------- Original Message -----------
>>>> From: B S
>>>>
>>>>> I want to capture 50 Hz signal with sampling frequency not more than 2
>>>>> kHz. I am using OMAP-L138 EVM with has ADS901 attached with it. It has
>>>>> sampling rate 20 MSPS, I can't get less than 212.60 kHz sampling rate
>>>>> because it uses programmable PLL (CDCE913) to set the clock. I will
>>>>> have to do downsampling which I haven't figured out yet.
>>>
>>> Most probably I have missed some bits of important information, but from
>>> what I can see now, why wouldn't one would use a slow audio type of an
>>> ADC device and McASP to read samples digitized at exactly Fs = 2,000Hz?
>>>
>>> I think there are plenty of such devices out there on the market and
>>> they must be much cheaper to purchase, rather than more expensive
>>> speedy device of 20,000,000Hz sampling rate...
>>>
>>> Using a right device one wouldn't have to employ a numerically expensive
>>> downsampling procedure that has to apply a digital filter to remove
>>> 19,999 samples and free the CPU to perform other important tasks...
>>>
>>> Have I rally missed something?
>>>
>>> Rgds,
>>>
>>> Andrew
_____________________________________
> Thanks for all your help. Unfortunately, I can't change
> the processor at this point so sticking with it is the only
> option.
>
> However, I appreciate your help with the following query.
>
> If sampling at 200kHz then capturing 1024 point data takes
> (1/200k * 1024 = 5.12 mSec). This way I know i need atleast
> 4 buffer of size 1024 to capture a 50 Hz cycle. In my case
> it's DMA which transfers data to CPU and it always takes 17
> CPU cycle. How would I know in this case that how much
> samples i need to get a 50 Hz cycle ?
4 samples.
-Jeff
> ________________________________
> From: Jeff Brower
> To: B S
> Cc: c...
> Sent: Friday, January 4, 2013 6:32 AM
> Subject: Re: [c6x] Re: SWI vs. TSK
>
> BAS-
>
> I know I mentioned this already... but... multicore.
>
> One core could be doing decimation, another one your processing.
>
> Check out C66x series. Cores share substantial onchip memory area. And all cores are floating-point.
>
> -Jeff
>
>>> Date: Thu, 3 Jan 2013 05:15:36 -0800 (PST)
>>> From: B S
>> Cc: Richard Williams
>>> Subject: Re: [c6x] Re: SWI vs. TSK
>>>
>>> I could have taken your suggestion if I had an option to use McASP or slower
>>> ADC. I have to use OMAP-L138 EVM with 20 MSPS ADC. One application of my
>>> project is dealing with 1 MHz signal which make sense to use that ADC. I have
>>> to deal with 50 Hz signal using the same device. Therefore, digital filtering
>>> + decimation is the only solution i see right now.
>>
>> Let me assume Fs is 2MHz to get a 1MHz band. Then, if CPU rate is 300MHz, you
>> get no more than 150 clocks to process a single sample in your 1MHz digitized
>> signal.
>>
>> Then, you may have to downsample it to 1KHz band, then you just need to take
>> one sample out of every 1,000, and filter out aliasing frequencies above 1KHz,
>> that is between 1KHz and 2MHz. I guess this is going to be a long filter.
>>
>> I think you will have to use more CPUs and also split the analog input signal
>> into 2 channels, one sampled at a high rate, the other at a slower rate. This
>> would remove downsampling and antialiasing filter out from your system.
>>
>>> BTW, do you have any idea how could I implement decimation filter
>>> (Butterworth or Chebyshev) in C ?
>>
>> I have seen a couple of windows programs on the net that design a digital
>> filter. They calculate coefficients for either FIR or IIR filter type,
>> whichever suits better for you system.
>>
>> Rgds,
>> Andrew
>>
>>> From: Andrew Nesterov
>> To: c...
>>> Sent: Wednesday, January 2, 2013 10:56 PM
>>> Subject: [c6x] Re: SWI vs. TSK
>>>
>>>
>>> Hi B.S.,
>>>
>>>> ---------- Original Message -----------
>>>> From: B S
>>>>
>>>>> I want to capture 50 Hz signal with sampling frequency not more than 2
>>>>> kHz. I am using OMAP-L138 EVM with has ADS901 attached with it. It has
>>>>> sampling rate 20 MSPS, I can't get less than 212.60 kHz sampling rate
>>>>> because it uses programmable PLL (CDCE913) to set the clock. I will
>>>>> have to do downsampling which I haven't figured out yet.
>>>
>>> Most probably I have missed some bits of important information, but from
>>> what I can see now, why wouldn't one would use a slow audio type of an
>>> ADC device and McASP to read samples digitized at exactly Fs = 2,000Hz?
>>>
>>> I think there are plenty of such devices out there on the market and
>>> they must be much cheaper to purchase, rather than more expensive
>>> speedy device of 20,000,000Hz sampling rate...
>>>
>>> Using a right device one wouldn't have to employ a numerically expensive
>>> downsampling procedure that has to apply a digital filter to remove
>>> 19,999 samples and free the CPU to perform other important tasks...
>>>
>>> Have I rally missed something?
>>>
>>> Rgds,
>>>
>>> Andrew
_____________________________________
