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I will be
working with a system using the TMS320C6711 that may have some severe
timing constraints associated with handling data from a non-interruptible
input. Serial communication to a host will occur on interruptible
inputs. The serial communication protocol that will be
implemented is already in use with a prior version of the system using
a different processor. This new system must conform to the old way of
handling communication to external devices.
What I may need to do is ensure the
interrupt handlers are designed such a way that the processor
does not take away too much time from the non-interruptible
input.
I would like to know if there is there a
mechanism I can use to assign a delay value for a SWI (Software Interupt) or
Trap so that the processor does not service an associated interrupt for a
specified number of cycles.
What I hope to do then is to be able to break
up a lengthy processing that must be done deterministically via interrupt
handlers into several smaller interrupt handlers delayed in time. That way
the processor can get back to normal processing in between each level of nested
software interrupt.
-Brad
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Q regarding SWI and/or Traps on the TMS320C6711
Started by ●November 21, 2000
