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Hello all! I have to program data transfers of consecutive blocks between a peripheral and SDRAM using EDMA on 'C6711 (in both directions). The peripheral (WIZnet i2Chip W3100A) has an 8-bit async interface, and SDRAM is 32-bit wide. As far as I know, working with SDRAM is more efficient when using successive 32-bit accesses, so ESIZE == 00 would be the best decision. But the size of data block can vary from dozens of bytes to 8 KB, and it isn't always divisible by 4. So, if I want to use 32-bit element size, I have to take care of a 0-3 bytes tale, using a chained EDMA transfer or a direct access to the memory (in last case I'll have performance problems with a cache, because SDRAM buffers are cleaned/flushed before transfers). The question: is a performance profit of using 32-bit accesses worth of taking additional care of data tail? By the way, in case of 32-bit element size peripheral's EMIF has to split every 32-bit access to four 8-bit accesses because of WIZnet's interface. Maybe, fast SDRAM accesses must be on successive CLKs, and this procedure will eat all the profit? Unfortunately, I'm extremely short in time, so I don't have an opportunity to experiment :(((( I suppose that everyone has to solve similar problems from time to time, and I'll be very grateful to any advice from experienced person. Maybe there are some other factors and even completely different approaches to this problem... Thanks in advance! -- Best regards, Pavel mailto: |
EDMA transfer elment size
Started by ●August 7, 2003
