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Hi All, I am trying to configure an Altera chip (Cyclon) through the JTAG interface. I need to configure it with a jam player. Has anyone ported the code for this to C6000? Do you know where I can find something like that? Thanks, Maoz Loants |
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jam player for Altera Cyclon on C6205
Started by ●April 22, 2004
Reply by ●April 22, 20042004-04-22
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Hi Maoz I have a C6x that boots an altera cyclone FPGA. I have attached a word document describing the process, and my source code interpretation of this. The word document I believe comes from an Altera app note. Hope this helps. Cheers Brett maozlo wrote: Hi All, I am trying to configure an Altera chip (Cyclon) through the JTAG interface. I need to configure it with a jam player. Has anyone ported the code for this to C6000? Do you know where I can find something like that? Thanks, Maoz Loants _____________________________________ Note: If you do a simple "reply" with your email client, only the author of this message will receive your answer. You need to do a "reply all" if you want your answer to be distributed to the entire group. _____________________________________ About this discussion group: To Join: Send an email to c...@yahoogroups.com To Post: Send an email to c...@yahoogroups.com To Leave: Send an email to c...@yahoogroups.com Archives: http://www.yahoogroups.com/group/c6x Other Groups: http://www.dsprelated.com Yahoo! Groups Links --
Brett Olsen
Senior DSP Design Engineer
Tait Electronics Ltd 535 Wairakei Rd Christchurch New Zealand Phone: (64) (3) 357
0766
Fax: (64) (3) 359 4632 Email: b...@tait.co.nz Post: PO Box 1645, Christchurch, NZ | |||
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#include <stdio.h> #include <file.h #define DIM(array_) (sizeof(array_)/sizeof(*(array_))) #include <mod_DigitalHardware.pkg //class mod_imageManager : public mod_imageManager::mod_imageManager() { return; } mod_imageManager::~mod_imageManager() { return; } bool_t mod_imageManager::UpdateFpgaImage() { return( true ); } bool_t mod_imageManager::Bootload_Fpga( void ) { // Get access to GPIO mod_gpio gpio; mod_flash flash; const unsigned *fid = (unsigned*)0xabdcef01; // Open the GPIO device gpio.open(); // Open the flash device flash.open( (void*)fid, fpga_image, (O_BINARY | O_RDONLY) ); unsigned fpga_status = gpio.read( FPGA_STATUS_INPUT ); // Set the yellow led on to test gpio.write( GPIO_ONE_LED_YELLOW, HIGH ); // Set the FPGA to be configured gpio.write( FPGA_CONFIG_OUTPUT, LOW ); for (unsigned delay = 0; delay < 2; delay++) { asm(" nop 9"); } gpio.write( FPGA_CONFIG_OUTPUT, HIGH ); // Wait for the status bit of the fpga to go high bool_t start_config = false; unsigned escape_counter = 0; while ( true ) { fpga_status = gpio.read( FPGA_STATUS_INPUT ); escape_counter++; if ( fpga_status == HIGH ) { break; } if (escape_counter > 30000) { return( false ); } // !!Error!! } uint8_t dclock; uint8_t d0; int bytes_read = 0; int bytes_written = 0; uint8_t fpga_value; unsigned num_read; // Program the FPGA while ( true ) { // Read a byte from the flash num_read = flash.read( (void*)fid, &fpga_value, 1 ); bytes_read++; // Have we reached the end of the file ?? if (num_read == 0) { printf( "Bootload FPGA: All %d Values Read\n", bytes_read ); break; } // "Clock" the data into the fpga unsigned i; unsigned data; //unsigned pinID = FPGA_DCLK_OUTPUT | FPGA_DATA0_OUTPUT; unsigned delay; for ( i=0; i<8; i++) { d0 = (fpga_value>>i) & 0x1; gpio.write( FPGA_DATA0_OUTPUT, d0 ); // write "0x" on [DCLK:DATA0] gpio.write( FPGA_DCLK_OUTPUT, LOW ); // write "0x" on [DCLK:DATA0] for (delay = 0; delay < 10; delay++) { asm(" nop 9"); } gpio.write( FPGA_DCLK_OUTPUT, HIGH ); // write "1x" on [DCLK:DATA0] // Put in a delay due to the rate of clocking this interface ~10MHz for (delay = 0; delay < 10; delay++) { asm(" nop 9"); } } // Check the status pin fpga_status = gpio.read( FPGA_STATUS_INPUT ); if ( !fpga_status ) { printf("Bootload FPGA: Status Error During Programming\n"); break; } } // Wait for the CONF pin of the FPGA to go high within 1mS unsigned fpga_config; while ( true ) { fpga_config = gpio.read( FPGA_CONF_DONE_INPUT ); escape_counter++; if ( fpga_config == HIGH ) { break; } if (escape_counter > 30000) { return( false ); } // !!Error!! } return( true ); } bool_t mod_imageManager::UpdateDspImage() { return( true ); } |
Reply by ●April 26, 20042004-04-26
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Hi Brett,
Thanks for the explanation. This does seem to help. What type of configuration file are you using?
Thanks, Maoz
-----Original
Message-----
Hi Maoz
-- Brett Olsen Senior DSP Design Engineer
Phone: (64) (3) 357 0766 |
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Reply by ●April 27, 20042004-04-27
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Hi Maoz The file format that I am using is the Tabular Text File format. A description of this can be found by searching Quartus using the phrase "Convert Programming Files command". I then used a text editor to rearrange the data to look like an array, and then included the array when compiling DSP code. Cheers, Brett maoz wrote:
--
Brett Olsen
Senior DSP Design Engineer
Tait Electronics Ltd 535 Wairakei Rd Christchurch New Zealand Phone: (64) (3) 357
0766
Fax: (64) (3) 359 4632 Email: b...@tait.co.nz Post: PO Box 1645, Christchurch, NZ |
