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Hi, This is regarding a problem that we are facing with our DSP TMS320C6416 Version E.When interfaced with the BU61580 ( Via EMIFB CE2 space, 16 bit interface,Asynchronous), the read operations from the BU occurr without any problems , with the CE going low for every read. But, with the write operation ,for successive write operations , the CE remains low.We have interfaced AOE of the DSP to the r/w bar of the BU. De-assertion of the CE is not happening after every write opearation.But , when alternate reads are inserted after every write operation , the BU gets written.Write also happens when delays(in the form of NOPS , around 500) are inserted.The solution to this problem is required very urgently , so awaiting your responses. Code snippets: CE2 config: EMIF input clock :120MHz;8.33ns (internal clock source) /* * BU is mapped to CE2 space of the DSP */ *(int*)CECTL2 = 0x30C10A19; *(short *)(BU_REG_BASE_ADDR + IMR_REG_ADDR1) = 0x0010; *(short *)(BU_REG_BASE_ADDR + IMR_REG_ADDR2) = 0x0110; *(short *)(BU_REG_BASE_ADDR + IMR_REG_ADDR3) = 0x1111; *(short *)(BU_REG_BASE_ADDR + IMR_REG_ADDR4) = 0xFFED; *(short *)(BU_REG_BASE_ADDR + IMR_REG_ADDR5) = 0x7856; Thanks and Best regards, Ramya |
TMS320c6416-BU61580 Problem
Started by ●November 26, 2004
Reply by ●November 28, 20042004-11-28
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Ramya- > This is regarding a problem that we are facing with our DSP > TMS320C6416 Version E.When interfaced with the BU61580 ( Via EMIFB > CE2 space, 16 bit interface,Asynchronous), the read operations from > the BU occurr without any problems , with the CE going low for every > read. But, with the write operation ,for successive write > operations , the CE remains low.We have interfaced AOE of the DSP to > the r/w bar of the BU. De-assertion of the CE is not happening after > every write opearation.But , when alternate reads are inserted after > every write operation , the BU gets written.Write also happens when > delays(in the form of NOPS , around 500) are inserted.The solution to > this problem is required very urgently , so awaiting your responses. The design flaw is that AWE should be used for R/W on the BU, and B-CE2 should be run to /CS on the BU. If the BU has an /OE pin, then use AOE, otherwise don't use it. -Jeff |
