FollowUp -> What can a DM642 Display Videoport prevent from sending data?
finally one step forward...:
The problem is caused by the missing initialization of the FPGA on the
EVM642 board. This is between the VideoPort and the SAA7105 video encoder.
If this FPGA is not initialized correctly, some clocks are missing and VP
dosent finish its reset... (see spru295.pdf)
Thomas --- Weitergeleitete Nachricht / Forwarded Message ---
Subject: [c6x] What can a DM642 Display Videoport prevent from sending data?
I use the EVM642 board with CCS 2.21. I try to configure port 2 DM642 as VGA
display port (using CSL). I have taken the example in appendix B.2 of
spru629.pdf as a base program to initialize the VP registers.
When the board is power cycled, using my initialization, VP doesnt start
outputting data, VDSTAT remains 0 (no line count...). When I download the
VGA_DISPLAY - example out file (shipped with EVM board, output of color
bars), the display starts. After downloading this VGA_DISPLAY example once,
I can reset the CPU in CCS and start the output with my program successfuly.
There is a bit somewhere in a register that is set by VGA_DISPLAY and that I
have forgotten to set (or that is not there in the spru629 appendix b.2
example). The setting of this bit also survives a ResetCPU by CCS.
Can anyone tell me the steps to activate the VP-display port (apart from
setting the framesize etc. parameters)? I my program there are the following actions to activate the VP-display
*) Enable Video Port in the PERCFG register (CHIP_config)
*) VP_open(2, 0)
The call of VP_Open with VP_OPEN_RESET doesnt return if I call VP_open(2,
VP_OPEN_RESET) after calling VP_open(0, VP_OPEN_RESET). Is there a reason
*) set VPRST bit in VPCTL to 1 (Reset Video Port)
*) set PEREN bit in PCR (Enable VideoPort)
*) set RSTCH bit in VDCTL to 1 (Reset VideoDisplayModule)
*) set other Bits in VPCTL and other registers like VDFRMSZ
*) set VPHLT bit in VPCTL to 1 (Clear VPHLT - enable Video Port)
what is missing?
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