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McBSP initialisation on 6713B

Started by Bernhard 'Gustl' Bauer May 12, 2005
Hi,

according to spra488c all McBSP registers should be programmed while
SGRSTST=RRST=XRST=0. But if I do so I'm not able to set FSRP (PCR)
to ACTIVELOW! But when I set RRST=1 it works. Any idea whats wrong? This
is how I do it:

MCBSP_configArgs(hMcbsp1,
/* SPCR Setup */
MCBSP_SPCR_RMK(
MCBSP_SPCR_FREE_YES, /* 1 */
MCBSP_SPCR_SOFT_DEFAULT, /* 0 */
MCBSP_SPCR_FRST_DEFAULT, /* 0 */
MCBSP_SPCR_GRST_DEFAULT, /* 0 */
MCBSP_SPCR_XINTM_XRDY, /* 00 */
MCBSP_SPCR_XSYNCERR_DEFAULT, /* 0 */
MCBSP_SPCR_XRST_DEFAULT, /* 0 */
MCBSP_SPCR_DLB_OFF, /* 0 */
MCBSP_SPCR_RJUST_RZF, /* 00 */
MCBSP_SPCR_CLKSTP_DISABLE, /* 0 */
MCBSP_SPCR_DXENA_OFF, /* 0 */
MCBSP_SPCR_RINTM_FRM, /* 00 */
MCBSP_SPCR_RSYNCERR_DEFAULT, /* 0 */
// MCBSP_SPCR_RRST_DEFAULT /* 0 */
MCBSP_SPCR_RRST_1 /* 1 */
),
/* RCR Setup */
MCBSP_RCR_RMK(
MCBSP_RCR_RPHASE_DUAL, /* 0 */
MCBSP_RCR_RFRLEN2_OF(0), /* 00000 */
MCBSP_RCR_RWDLEN2_8BIT, /* 000 */
MCBSP_RCR_RCOMPAND_MSB, /* 00 */
MCBSP_RCR_RFIG_YES, /* 1 */
MCBSP_RCR_RDATDLY_1BIT, /* 01 */
MCBSP_RCR_RFRLEN1_OF(8), /* 01000 */
MCBSP_RCR_RWDLEN1_16BIT, /* 010 */
MCBSP_RCR_RWDREVRS_DISABLE /* 0 */
),
/* XCR Setup */
MCBSP_XCR_RMK(
MCBSP_XCR_XPHASE_DUAL, /* 1 */
MCBSP_XCR_XFRLEN2_OF(0), /* 00000 */
MCBSP_XCR_XWDLEN2_16BIT, /* 010 */
MCBSP_XCR_XCOMPAND_MSB, /* 00 */
MCBSP_XCR_XFIG_YES, /* 1 */
MCBSP_XCR_XDATDLY_0BIT, /* 00 */
MCBSP_XCR_XFRLEN1_OF(8), /* 01000 */
MCBSP_XCR_XWDLEN1_16BIT, /* 010 */
MCBSP_XCR_XWDREVRS_DISABLE /* 0 */
),
/* SRGR Setup */
MCBSP_SRGR_RMK(
MCBSP_SRGR_GSYNC_FREE, /* 0 */
MCBSP_SRGR_CLKSP_RISING, /* 0 */
MCBSP_SRGR_CLKSM_CLKS, /* 0 */
MCBSP_SRGR_FSGM_DXR2XSR, /* 0 */
MCBSP_SRGR_FPER_DEFAULT, /* 0 */
MCBSP_SRGR_FWID_DEFAULT, /* 0 */
MCBSP_SRGR_CLKGDV_OF(BAUDDIV1) /* CLKGDV */
),
/* MCR Setup */
MCBSP_MCR_DEFAULT, /* default values */
/* RCER Setup */
MCBSP_RCER_DEFAULT, /* default values */
/* XCER Setup */
MCBSP_XCER_DEFAULT, /* default values */
/* PCR Setup */
MCBSP_PCR_RMK(
MCBSP_PCR_XIOEN_GPIO, /* 0 */
MCBSP_PCR_RIOEN_GPIO, /* 0 */
MCBSP_PCR_FSXM_INTERNAL, /* 1 */
MCBSP_PCR_FSRM_EXTERNAL, /* 0 */
MCBSP_PCR_CLKXM_OUTPUT, /* 1 */
MCBSP_PCR_CLKRM_OUTPUT, /* 1 */
MCBSP_PCR_CLKSSTAT_0, /* 0 */
MCBSP_PCR_DXSTAT_0, /* 0 */
MCBSP_PCR_FSXP_ACTIVEHIGH, /* 0 */
MCBSP_PCR_FSRP_ACTIVELOW, /* 1 */
MCBSP_PCR_CLKXP_RISING, /* 0 */
MCBSP_PCR_CLKRP_FALLING /* 0 */
)
);