Looking at the schematic for the EVMDM642 from TI, I see the following
connections between the DSP and SDRAM chips.
DSP SDRAM #1
D0 --\ /---------- D0
\ /
/ \
D7----/ \--------- D7
D8----------------------D8
D15---------------------D15
D16 --\ /---------- D16
\ /
/ \
D23----/ \--------- D23
D24----------------------D24
D31---------------------D31
So, D8-D16 feed through directly as do D24-D31 but D0-6 and D16-23 are inverted
on a byte level.
Does anyone have any idea why this is so?
I started to think about endianess, but am not convinced that this is the
solution. Could it be that the circuit schematic is incorrect?
Many thanks,
Stephen.
EVMDM642 and SDRAM
Started by ●June 13, 2005
Reply by ●June 13, 20052005-06-13
Stephen-
> Looking at the schematic for the EVMDM642 from TI, I see the following connections between the DSP and SDRAM chips.
>
> DSP SDRAM #1
>
> D0 --\ /---------- D0
> \ /
> / \
> D7----/ \--------- D7
>
> D8----------------------D8
>
> D15---------------------D15
>
> D16 --\ /---------- D16
> \ /
> / \
> D23----/ \--------- D23
>
> D24----------------------D24
>
> D31---------------------D31
>
> So, D8-D16 feed through directly as do D24-D31 but D0-6 and D16-23 are inverted on a byte level.
>
> Does anyone have any idea why this is so?
>
> I started to think about endianess, but am not convinced that this is the solution. Could it be that the circuit schematic is incorrect?
Probably just to make routing easier. For each byte as long as data comes out the
way it went in, then no worry. It would matter if the SDRAM was shared with another
device that hooked up differently, but not the case on the EVM DM642.
-Jeff
> Looking at the schematic for the EVMDM642 from TI, I see the following connections between the DSP and SDRAM chips.
>
> DSP SDRAM #1
>
> D0 --\ /---------- D0
> \ /
> / \
> D7----/ \--------- D7
>
> D8----------------------D8
>
> D15---------------------D15
>
> D16 --\ /---------- D16
> \ /
> / \
> D23----/ \--------- D23
>
> D24----------------------D24
>
> D31---------------------D31
>
> So, D8-D16 feed through directly as do D24-D31 but D0-6 and D16-23 are inverted on a byte level.
>
> Does anyone have any idea why this is so?
>
> I started to think about endianess, but am not convinced that this is the solution. Could it be that the circuit schematic is incorrect?
Probably just to make routing easier. For each byte as long as data comes out the
way it went in, then no worry. It would matter if the SDRAM was shared with another
device that hooked up differently, but not the case on the EVM DM642.
-Jeff
Reply by ●June 13, 20052005-06-13
Hello Stephen,
Short answer:
I haven't looked at the specifics, but I am about 99% sure that it is
for hardware convenience [simpler routing of the signals] and really
doesn't matter.
Long Answer:
First let us consider a simple example. I have a ram chip that has 16
locations that are four bits wide. we know that RAM chips data is of no use
until it is written. I mix up my 4 address lines [any way you like] and
then i mix up my four data lines [again, anyway you like]. As long as i
don't change the physical connections, the data pattern that i write for
address 0010, will also be read back for that address. The bottom line is
that the connections do not matter - as long as i have address lines to address
pins and data lines to data pins. The a0, a1, a2... designations are for
convenience [and data sheet clarity] only in the example above.
The "don't care swapping rules" are slightly more complicated for
SDRAMs, but they are conceptually the same.
I hope that i didn't bore you...
mikedunn
s...@unn.ac.uk wrote:
s...@unn.ac.uk wrote:
Looking at the schematic for the EVMDM642 from TI, I see the following connections between the DSP and SDRAM chips.DSP SDRAM #1
D0 --\ /---------- D0
\ /
/ \
D7----/ \--------- D7
D8----------------------D8D15---------------------D15
D16 --\ /---------- D16
\ /
/ \
D23----/ \--------- D23D24----------------------D24D31---------------------D31
So, D8-D16 feed through directly as do D24-D31 but D0-6 and D16-23 are inverted on a byte level.
Does anyone have any idea why this is so?
I started to think about endianess, but am not convinced that this is the solution. Could it be that the circuit schematic is incorrect?Many thanks,Stephen.
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Reply by ●June 14, 20052005-06-14
You are absolutely right Mike,
It is indeep for hardware convenience...
Regards,
Kalpesh.
----- Original Message -----
From: Mike Dunn
To: stephen.ormston@step... ; c6x@c6x@...
Sent: Tuesday, June 14, 2005 8:07 AM
Subject: Re: [c6x] EVMDM642 and SDRAM Hello Stephen,
Short answer:
I haven't looked at the specifics, but I am about 99% sure that it is for hardware convenience [simpler routing of the signals] and really doesn't matter.
Long Answer:
First let us consider a simple example. I have a ram chip that has 16 locations that are four bits wide. we know that RAM chips data is of no use until it is written. I mix up my 4 address lines [any way you like] and then i mix up my four data lines [again, anyway you like]. As long as i don't change the physical connections, the data pattern that i write for address 0010, will also be read back for that address. The bottom line is that the connections do not matter - as long as i have address lines to address pins and data lines to data pins. The a0, a1, a2... designations are for convenience [and data sheet clarity] only in the example above.
The "don't care swapping rules" are slightly more complicated for SDRAMs, but they are conceptually the same.
I hope that i didn't bore you...
mikedunn
stephen.ormston@step... wrote:
Looking at the schematic for the EVMDM642 from TI, I see the following connections between the DSP and SDRAM chips. DSP SDRAM #1
D0 --\ /---------- D0
\ /
/ \
D7----/ \--------- D7
D8----------------------D8 D15---------------------D15
D16 --\ /---------- D16
\ /
/ \
D23----/ \--------- D23 D24----------------------D24 D31---------------------D31
So, D8-D16 feed through directly as do D24-D31 but D0-6 and D16-23 are inverted on a byte level.
Does anyone have any idea why this is so?
I started to think about endianess, but am not convinced that this is the solution. Could it be that the circuit schematic is incorrect? Many thanks, Stephen.
a.. To
It is indeep for hardware convenience...
Regards,
Kalpesh.
----- Original Message -----
From: Mike Dunn
To: stephen.ormston@step... ; c6x@c6x@...
Sent: Tuesday, June 14, 2005 8:07 AM
Subject: Re: [c6x] EVMDM642 and SDRAM Hello Stephen,
Short answer:
I haven't looked at the specifics, but I am about 99% sure that it is for hardware convenience [simpler routing of the signals] and really doesn't matter.
Long Answer:
First let us consider a simple example. I have a ram chip that has 16 locations that are four bits wide. we know that RAM chips data is of no use until it is written. I mix up my 4 address lines [any way you like] and then i mix up my four data lines [again, anyway you like]. As long as i don't change the physical connections, the data pattern that i write for address 0010, will also be read back for that address. The bottom line is that the connections do not matter - as long as i have address lines to address pins and data lines to data pins. The a0, a1, a2... designations are for convenience [and data sheet clarity] only in the example above.
The "don't care swapping rules" are slightly more complicated for SDRAMs, but they are conceptually the same.
I hope that i didn't bore you...
mikedunn
stephen.ormston@step... wrote:
Looking at the schematic for the EVMDM642 from TI, I see the following connections between the DSP and SDRAM chips. DSP SDRAM #1
D0 --\ /---------- D0
\ /
/ \
D7----/ \--------- D7
D8----------------------D8 D15---------------------D15
D16 --\ /---------- D16
\ /
/ \
D23----/ \--------- D23 D24----------------------D24 D31---------------------D31
So, D8-D16 feed through directly as do D24-D31 but D0-6 and D16-23 are inverted on a byte level.
Does anyone have any idea why this is so?
I started to think about endianess, but am not convinced that this is the solution. Could it be that the circuit schematic is incorrect? Many thanks, Stephen.
a.. To
Reply by ●June 14, 20052005-06-14
Many thanks to all for the quick reply.
What you say makes complete sense and I will have more confidence in the
design now.
Thanks again,
Stephen.
-----Original Message-----
From: Kalpesh Chauhan [mailto:kalpesh.chauhan@kalp...]
Sent: 14 June 2005 07:13
To: stephen.ormston; c6x; Mike Dunn
Subject: Re: [c6x] EVMDM642 and SDRAM You are absolutely right Mike,
It is indeep for hardware convenience...
Regards,
Kalpesh.
----- Original Message -----
From: Mike <mailto:mike-dunn@mike...> Dunn
To: stephen.ormston@step... <mailto:stephen.ormston@step...> ;
c6x@c6x@... <mailto:c6x@c6x@...>
Sent: Tuesday, June 14, 2005 8:07 AM
Subject: Re: [c6x] EVMDM642 and SDRAM
Hello Stephen,
Short answer:
I haven't looked at the specifics, but I am about 99% sure that it is for
hardware convenience [simpler routing of the signals] and really doesn't
matter.
Long Answer:
First let us consider a simple example. I have a ram chip that has 16
locations that are four bits wide. we know that RAM chips data is of no use
until it is written. I mix up my 4 address lines [any way you like] and
then i mix up my four data lines [again, anyway you like]. As long as i
don't change the physical connections, the data pattern that i write for
address 0010, will also be read back for that address. The bottom line is
that the connections do not matter - as long as i have address lines to
address pins and data lines to data pins. The a0, a1, a2... designations
are for convenience [and data sheet clarity] only in the example above.
The "don't care swapping rules" are slightly more complicated for SDRAMs,
but they are conceptually the same.
I hope that i didn't bore you...
mikedunn
stephen.ormston@step... wrote:
Looking at the schematic for the EVMDM642 from TI, I see the following
connections between the DSP and SDRAM chips. DSP SDRAM #1
D0 --\ /---------- D0
\ /
/ \
D7----/ \--------- D7
D8----------------------D8 D15---------------------D15
D16 --\ /---------- D16
\ /
/ \
D23----/ \--------- D23 D24----------------------D24 D31---------------------D31
So, D8-D16 feed through directly as do D24-D31 but D0-6 and D16-23 are
inverted on a byte level.
Does anyone have any idea why this is so?
I started to think about endianess, but am not convinced that this is the
solution. Could it be that the circuit schematic is incorrect? Many thanks, Stephen.
* To br> <http://docs.yahoo.com/info/terms/> .
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What you say makes complete sense and I will have more confidence in the
design now.
Thanks again,
Stephen.
-----Original Message-----
From: Kalpesh Chauhan [mailto:kalpesh.chauhan@kalp...]
Sent: 14 June 2005 07:13
To: stephen.ormston; c6x; Mike Dunn
Subject: Re: [c6x] EVMDM642 and SDRAM You are absolutely right Mike,
It is indeep for hardware convenience...
Regards,
Kalpesh.
----- Original Message -----
From: Mike <mailto:mike-dunn@mike...> Dunn
To: stephen.ormston@step... <mailto:stephen.ormston@step...> ;
c6x@c6x@... <mailto:c6x@c6x@...>
Sent: Tuesday, June 14, 2005 8:07 AM
Subject: Re: [c6x] EVMDM642 and SDRAM
Hello Stephen,
Short answer:
I haven't looked at the specifics, but I am about 99% sure that it is for
hardware convenience [simpler routing of the signals] and really doesn't
matter.
Long Answer:
First let us consider a simple example. I have a ram chip that has 16
locations that are four bits wide. we know that RAM chips data is of no use
until it is written. I mix up my 4 address lines [any way you like] and
then i mix up my four data lines [again, anyway you like]. As long as i
don't change the physical connections, the data pattern that i write for
address 0010, will also be read back for that address. The bottom line is
that the connections do not matter - as long as i have address lines to
address pins and data lines to data pins. The a0, a1, a2... designations
are for convenience [and data sheet clarity] only in the example above.
The "don't care swapping rules" are slightly more complicated for SDRAMs,
but they are conceptually the same.
I hope that i didn't bore you...
mikedunn
stephen.ormston@step... wrote:
Looking at the schematic for the EVMDM642 from TI, I see the following
connections between the DSP and SDRAM chips. DSP SDRAM #1
D0 --\ /---------- D0
\ /
/ \
D7----/ \--------- D7
D8----------------------D8 D15---------------------D15
D16 --\ /---------- D16
\ /
/ \
D23----/ \--------- D23 D24----------------------D24 D31---------------------D31
So, D8-D16 feed through directly as do D24-D31 but D0-6 and D16-23 are
inverted on a byte level.
Does anyone have any idea why this is so?
I started to think about endianess, but am not convinced that this is the
solution. Could it be that the circuit schematic is incorrect? Many thanks, Stephen.
* To br> <http://docs.yahoo.com/info/terms/> .
--
This message has been scanned for viruses and dangerous
content by the NorMAN <http://www.mailscanner.info/> MailScanner Service
and is believed
to be clean.
The NorMAN MailScanner Service is operated by Information
Systems and Services, University of Newcastle upon Tyne.
====
This e-mail is intended solely for the addressee. It may contain private and
confidential information. If you are not the intended addressee, please take
no action based on it nor show a copy to anyone. Please reply to this e-mail
to highlight the error. You should also be aware that all electronic mail
from, to, or within Northumbria University may be the subject of a request
under the Freedom of Information Act 2000 and related legislation, and
therefore may be required to be disclosed to third parties.
This e-mail and attachments have been scanned for viruses prior to leaving
Northumbria University. Northumbria University will not be liable for any
losses as a result of any viruses being passed on.
