Hi,
I am trying to understand
the working of McBsp working and so i took this code
from SPRA636a.pdf which uses McBsp/EDMA for non busrt
peripheral data transfer. I find that on compilation
and execution it does not work as expected. Moreover I
find channel 12 and channel 13 has been interchanged
for receive and transmit resply. I am attacihng the
code for you to see. Can you tell me where i could be
wrong. I want to do a loopback operation and see it
work.Please let me know
/********************************************************************************/
/* nb_perph.c */
/* written by David Bell */
/* on 12/20/00 */
/* */
/* nb_perph uses two EDMA channels to service McBSP0.
Channel 12 is used to */
/* transmit a frame of data from L2 to the DXR.
Channel 13 is used to transmit */
/* a frame of data from the DRR to L2. */
/********************************************************************************/
#include <csl.h>
#include <csl_edma.h>
#include <csl_mcbsp.h>
/* definitions */
#define MEM_SRC 0x80000000 /* Source address for
transfer */
#define MEM_DST 0x00008000 /* Destination address for
transfer */
#define EL_COUNT 0x0100 /* Element count for transfer
*/
/* prototypes */
void cfg_data(void);
Int32 cfg_edma(EDMA_Handle *hEdma_ch12, EDMA_Handle
*hEdma_ch13);
void wait(void);
Int32 check_data(void);
extern void cfg_mcbsp(MCBSP_Handle *hMcbsp_ch0);
extern void start_mcbsp(MCBSP_Handle *hMcbsp_ch0);
/************************************cfg_data************************************/
/* Store a data ramp in the source memory space. This
data will be transferred */
/* by the EDMA. */
/********************************************************************************/
void cfg_data()
{
unsigned short *val;
unsigned short i = 0;
val = (unsigned short *)MEM_SRC;
/* Set up transfer data */
for (i = 0; i < (EL_COUNT<<1); i++)
{
*val++ = i;
} /* end for */
} /* end cfg_data */
/*************************************cfg_edma***********************************/
/* Program EDMA channels 12 and 13 to service McBSP0.
Both channels terminate */
/* by linking to a NULL parameter set. */
/********************************************************************************/
Int32 cfg_edma(EDMA_Handle *hEdma_ch12, EDMA_Handle
*hEdma_ch13)
{
Uint32 link_address;
EDMA_Config config;
EDMA_Handle hEdma_NULL;
if (!EDMA_allocTableEx(1, &hEdma_NULL)) return(-1);
EDMA_reset(hEdma_NULL);
link_address = EDMA_getTableAddress(hEdma_NULL);
*hEdma_ch12 = EDMA_open(12, EDMA_OPEN_RESET);
*hEdma_ch13 = EDMA_open(13, EDMA_OPEN_RESET);
/* Configure the transmit channel (13) */
config.opt = (Uint32) /* 0xA0000000 */
((EDMA_OPT_PRI_HIGH << _EDMA_OPT_PRI_SHIFT )
| (EDMA_OPT_ESIZE_32BIT << _EDMA_OPT_ESIZE_SHIFT )
| (EDMA_OPT_2DS_NO << _EDMA_OPT_2DS_SHIFT )
| (EDMA_OPT_SUM_INC << _EDMA_OPT_SUM_SHIFT )
| (EDMA_OPT_2DD_NO << _EDMA_OPT_2DD_SHIFT )
| (EDMA_OPT_DUM_NONE << _EDMA_OPT_DUM_SHIFT )
| (EDMA_OPT_TCINT_YES << _EDMA_OPT_TCINT_SHIFT )
| (EDMA_OPT_TCC_OF(13) << _EDMA_OPT_TCC_SHIFT )
#if (C64_SUPPORT)
| (EDMA_OPT_TCCM_DEFAULT << _EDMA_OPT_TCCM_SHIFT )
| (EDMA_OPT_ATCINT_NO << _EDMA_OPT_ATCINT_SHIFT)
| (EDMA_OPT_ATCC_DEFAULT << _EDMA_OPT_ATCC_SHIFT )
| (EDMA_OPT_PDTS_DISABLE << _EDMA_OPT_PDTS_SHIFT )
| (EDMA_OPT_PDTD_DISABLE << _EDMA_OPT_PDTD_SHIFT )
#endif
| (EDMA_OPT_LINK_YES << _EDMA_OPT_LINK_SHIFT )
| (EDMA_OPT_FS_NO << _EDMA_OPT_FS_SHIFT ));
config.src = (Uint32)MEM_SRC; /* 0xA0000000 */
config.cnt = (Uint32)EL_COUNT; /* 0x00000100 */
config.dst = (Uint32)_MCBSP_DXR0_ADDR; /* 0x30000000
*/
config.idx = (Uint32)0; /* 0x00000000 */
config.rld = (Uint32)link_address & 0xffff; /* &NULL
*/
EDMA_config(*hEdma_ch12, &config);
config.opt = (Uint32) /* 0xA0000000 */
((EDMA_OPT_PRI_HIGH << _EDMA_OPT_PRI_SHIFT )
| (EDMA_OPT_ESIZE_32BIT << _EDMA_OPT_ESIZE_SHIFT )
| (EDMA_OPT_2DS_NO << _EDMA_OPT_2DS_SHIFT )
| (EDMA_OPT_SUM_NONE << _EDMA_OPT_SUM_SHIFT )
| (EDMA_OPT_2DD_NO << _EDMA_OPT_2DD_SHIFT )
| (EDMA_OPT_DUM_INC << _EDMA_OPT_DUM_SHIFT )
| (EDMA_OPT_TCINT_YES << _EDMA_OPT_TCINT_SHIFT )
| (EDMA_OPT_TCC_OF(12) << _EDMA_OPT_TCC_SHIFT )
#if (C64_SUPPORT)
| (EDMA_OPT_TCCM_DEFAULT << _EDMA_OPT_TCCM_SHIFT )
| (EDMA_OPT_ATCINT_NO << _EDMA_OPT_ATCINT_SHIFT)
| (EDMA_OPT_ATCC_DEFAULT << _EDMA_OPT_ATCC_SHIFT )
| (EDMA_OPT_PDTS_DISABLE << _EDMA_OPT_PDTS_SHIFT )
| (EDMA_OPT_PDTD_DISABLE << _EDMA_OPT_PDTD_SHIFT )
#endif
| (EDMA_OPT_LINK_YES << _EDMA_OPT_LINK_SHIFT )
| (EDMA_OPT_FS_NO << _EDMA_OPT_FS_SHIFT ));
config.src = (Uint32)_MCBSP_DRR0_ADDR; /* 0x30000000
*/
config.cnt = (Uint32)EL_COUNT; /* 0x00000100 */
config.dst = (Uint32)MEM_DST; /* 0x00009000 */
config.idx = (Uint32)0; /* 0x00000000 */
config.rld = (Uint32)link_address & 0xffff; /* &NULL
*/
EDMA_config(*hEdma_ch13, &config);
return(0);
} /* end cfg_edma */
/**************************************wait**************************************/
/* Wait until the transfer completes, as indicated by
bit 12 of the Channel */
/* Interrupt Pending Register (CIPR). */
/********************************************************************************/
void wait(void)
{
while (!((Uint32)EDMA_RGET(CIPR) & (1 << 12)));
} /* end wait */
/***********************************check_data***********************************/
/* Verify that the data was properly transferred by
comparing the source data */
/* to the destination data. */
/********************************************************************************/
int
check_data(void)
{
unsigned short *src = (unsigned short *)MEM_SRC,
*dst = (unsigned short *)MEM_DST,
source = 0,
dest = 0;
short i = 0;
int err = 0;
for (i = 0; i < (EL_COUNT<<1); i++)
{
dest = *dst;
source = *src;
if (dest != source)
{
/* Set error value if incorrect data */
err = i;
break;
} /* end if */
dst += 1;
src += 1;
} /* end for i */
return(err);
} /* end check_data */
/**************************************main**************************************/
/* Main code body. */
/********************************************************************************/
void
main(void)
{
Uint32 error = 0;
EDMA_Handle hEdma_ch12;
EDMA_Handle hEdma_ch13;
MCBSP_Handle hMcbsp_ch0;
MCBSP_resetAll();
EDMA_resetAll();
cfg_data();
error = cfg_edma(&hEdma_ch12, &hEdma_ch13);
if (!error)
{
EDMA_intClear(13);
cfg_mcbsp(&hMcbsp_ch0);
EDMA_enableChannel(hEdma_ch12);
EDMA_enableChannel(hEdma_ch13);
start_mcbsp(&hMcbsp_ch0);
wait();
EDMA_close(hEdma_ch12);
EDMA_close(hEdma_ch13);
MCBSP_close(hMcbsp_ch0);
} /* end if !error */
if (!error) error = check_data();
while(error);
while(!error);
} /* end main */
/********************************************************************************/
/* Project: EDMA Test */
/* mcbsp.c */
/* written by David Bell */
/* on 6/21/99 */
/* */
/* mcbsp.c configures the McBSPs as required for the
EDMA transfers on channels */
/* 12 15. The McBSP in use is configured to operate
in digital loopback (DLB) */
/* mode, such that the data transferred is looped back
to the receive port in */
/* ternally. */
/* */
/********************************************************************************/
#include <csl.h>
#include <csl_mcbsp.h>
/* prototypes */
void cfg_mcbsp(MCBSP_Handle *hMcbsp_ch0);
void start_mcbsp(MCBSP_Handle *hMcbsp_ch0);
/***********************************cfg_mcbsp************************************/
/* Program McBSP0 to transmit and receive 32bit
elements in digital loopback. */
/********************************************************************************/
void cfg_mcbsp(MCBSP_Handle *hMcbsp_ch0)
{
MCBSP_Config config;
*hMcbsp_ch0 = MCBSP_open(0, MCBSP_OPEN_RESET);
/* Set up Serial Port Control Register */
config.spcr = (Uint32)
((MCBSP_SPCR_XINTM_XRDY << _MCBSP_SPCR_XINTM_SHIFT)
| (MCBSP_SPCR_RINTM_RRDY << _MCBSP_SPCR_RINTM_SHIFT)
| (MCBSP_SPCR_DLB_ON << _MCBSP_SPCR_DLB_SHIFT ));
/* Set up Pin Control Register */
config.pcr = (Uint32)
((MCBSP_PCR_FSXM_INTERNAL << _MCBSP_PCR_FSXM_SHIFT)
| (MCBSP_PCR_FSRM_INTERNAL << _MCBSP_PCR_FSXM_SHIFT)
| (MCBSP_PCR_CLKXM_OUTPUT << _MCBSP_PCR_CLKXM_SHIFT)
| (MCBSP_PCR_CLKRM_OUTPUT << _MCBSP_PCR_CLKRM_SHIFT)
| (MCBSP_PCR_FSXP_ACTIVEHIGH <<
_MCBSP_PCR_FSXP_SHIFT)
| (MCBSP_PCR_FSRP_ACTIVEHIGH <<
_MCBSP_PCR_FSRP_SHIFT)
| (MCBSP_PCR_CLKXP_RISING << _MCBSP_PCR_CLKXP_SHIFT)
| (MCBSP_PCR_CLKRP_FALLING <<
_MCBSP_PCR_CLKRP_SHIFT));
/* Set up Receive Control Register */
config.rcr = (Uint32)
((MCBSP_RCR_RPHASE_SINGLE << _MCBSP_RCR_RPHASE_SHIFT
)
| (MCBSP_RCR_RFIG_YES << _MCBSP_RCR_RFIG_SHIFT )
| (MCBSP_RCR_RDATDLY_1BIT <<
_MCBSP_RCR_RDATDLY_SHIFT )
| (MCBSP_RCR_RFRLEN1_OF(0) <<
_MCBSP_RCR_RFRLEN1_SHIFT )
| (MCBSP_RCR_RWDLEN1_32BIT <<
_MCBSP_RCR_RWDLEN1_SHIFT )
| (MCBSP_RCR_RCOMPAND_MSB <<
_MCBSP_RCR_RCOMPAND_SHIFT));
/* Set up Transmit Control Register */
config.xcr = (Uint32)
((MCBSP_XCR_XPHASE_SINGLE << _MCBSP_XCR_XPHASE_SHIFT
)
| (MCBSP_XCR_XFIG_YES << _MCBSP_XCR_XFIG_SHIFT )
| (MCBSP_XCR_XDATDLY_1BIT <<
_MCBSP_XCR_XDATDLY_SHIFT )
| (MCBSP_XCR_XFRLEN1_OF(0) <<
_MCBSP_XCR_XFRLEN1_SHIFT )
| (MCBSP_XCR_XWDLEN1_32BIT <<
_MCBSP_XCR_XWDLEN1_SHIFT )
| (MCBSP_XCR_XCOMPAND_MSB <<
_MCBSP_XCR_XCOMPAND_SHIFT));
/* Set up Sample Rate Generator Register */
config.srgr = (Uint32)
((MCBSP_SRGR_CLKSM_INTERNAL <<
_MCBSP_SRGR_CLKSM_SHIFT )
| (MCBSP_SRGR_FSGM_DXR2XSR << _MCBSP_SRGR_FSGM_SHIFT
)
| (MCBSP_SRGR_CLKGDV_OF(7) <<
_MCBSP_SRGR_CLKGDV_SHIFT));
MCBSP_config(*hMcbsp_ch0, &config);
} /* end config_mcbsp */
void start_mcbsp(MCBSP_Handle *hMcbsp_ch0)
{
/* Bring McBSPs out of reset */
MCBSP_enableSrgr(*hMcbsp_ch0); /* Start Sample Rate
Generator */
MCBSP_enableFsync(*hMcbsp_ch0); /* Enable Frame Sync
pulse */
MCBSP_enableRcv(*hMcbsp_ch0); /* Bring Receive out of
reset */
MCBSP_enableXmt(*hMcbsp_ch0); /* Bring Transmit out
of reset */
} /* end start_mcbsp */
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