Dm642: EDMA problem
Started by ●June 30, 2005
Hi All,
I have configured an EDMA channel Rcv data from the McASP. My aim is
to get some 80 samples in a buffer and then send an interrupt to the CPU.
The EDMA successfully transfers one sample at a time and generates a
CPU interrupt after each sample. I have a very basic question: Is it
possible to buffer 80 samples before sending a CPU interrupt? If yes,
what am I doing wrong?
I followed the sprc090 CSL example and have configured the McASP for
Burst transfer. This is how my EDMA Rcv config looks like:
EDMA_configArgs
(
hEdmaAREVT,
EDMA_OPT_RMK
(
EDMA_OPT_PRI_HIGH,
EDMA_OPT_ESIZE_32BIT,
EDMA_OPT_2DS_NO,
EDMA_OPT_SUM_IDX,
EDMA_OPT_2DD_NO,
EDMA_OPT_DUM_NONE,
EDMA_OPT_TCINT_YES,
EDMA_OPT_TCC_OF(EDMA_CHA_AREVT0),
EDMA_OPT_TCCM_OF(EDMA_CHA_AREVT0 >> 4),
EDMA_OPT_ATCINT_NO,
EDMA_OPT_ATCC_OF(0),
EDMA_OPT_PDTS_DISABLE,
EDMA_OPT_PDTD_DISABLE,
EDMA_OPT_LINK_YES,
EDMA_OPT_FS_YES
),
EDMA_SRC_RMK(MCASP_getRbufAddr(hMcasp)),
EDMA_CNT_RMK(80, 1), //Frame size, element size
EDMA_DST_RMK((Uint32)Rcvdata),
EDMA_IDX_RMK(EDMA_IDX_FRMIDX_DEFAULT,EDMA_IDX_ELEIDX_DEFAULT),
EDMA_RLD_RMK(1,0)
);
EDMA_link(hEdmaAREVT, hEdmaAREVT);
EDMA_intHook(EDMA_CHA_AXEVT0, setRcvDone1);
)
(As of now the setRcvDone1 ISR doesn't do anything). I have tried with
no Frame Sync, and also with Framesize =1 and Element size = 80...,
but nothing seems to work for multiple samples.
I "View Memory" or LOG_printf the Rcvdata and find only one sample
changing value whatever I do...
Thanks a lot in advance.
Regards
Suba.
Reply by ●July 1, 20052005-07-01
> -----Original Message-----
> From: c6x@c6x@... [mailto:c6x@c6x@...] On Behalf Of
> ravibsuba
> Sent: Thursday, June 30, 2005 5:36 AM
> To: c6x@c6x@...
> Subject: [c6x] Dm642: EDMA problem > Hi All,
>
> I have configured an EDMA channel Rcv data from the McASP. My aim is
> to get some 80 samples in a buffer and then send an interrupt to the CPU.
>
> The EDMA successfully transfers one sample at a time and generates a
> CPU interrupt after each sample. I have a very basic question: Is it
> possible to buffer 80 samples before sending a CPU interrupt? If yes,
> what am I doing wrong?
Think there's an option in the EDMA to not get an interrupt until it's
complete a frame or block size. Guess you could define one of those to be
80 samples.
Robert
www.gldsp.com
--
No virus found in this outgoing message.
Checked by AVG Anti-Virus.
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Reply by ●July 2, 20052005-07-02
Thanks Robert. From what I understand from the spru234 document,
the interrupt will be generated only at the end of all the transfers
(i.e. all frames). There is an option to generate the interrupt at the
end of each frame by configuring the ATCC bit.
Probably the problem is due to the McASP... since it has an
XBUF/RBUF of size only 32 bits??? --- In c6x@c6x@..., "robert" <r_obert@h...> wrote:
>
>
> > -----Original Message-----
> > From: c6x@c6x@... [mailto:c6x@c6x@...] On Behalf Of
> > ravibsuba
> > Sent: Thursday, June 30, 2005 5:36 AM
> > To: c6x@c6x@...
> > Subject: [c6x] Dm642: EDMA problem
> >
> >
> > Hi All,
> >
> > I have configured an EDMA channel Rcv data from the McASP. My aim is
> > to get some 80 samples in a buffer and then send an interrupt to
the CPU.
> >
> > The EDMA successfully transfers one sample at a time and generates a
> > CPU interrupt after each sample. I have a very basic question: Is it
> > possible to buffer 80 samples before sending a CPU interrupt? If yes,
> > what am I doing wrong? > Think there's an option in the EDMA to not get an interrupt until it's
> complete a frame or block size. Guess you could define one of those
to be
> 80 samples.
>
> Robert
>
> www.gldsp.com
>
> --
> No virus found in this outgoing message.
> Checked by AVG Anti-Virus.
> Version: 7.0.323 / Virus Database: 267.8.6/33 - Release Date: 6/28/2005
Reply by ●July 4, 20052005-07-04
> -----Original Message-----
> From: c6x@c6x@... [mailto:c6x@c6x@...] On Behalf Of
> ravibsuba
> Sent: Saturday, July 02, 2005 1:11 AM
> To: c6x@c6x@...
> Subject: [c6x] Re: Dm642: EDMA problem > Thanks Robert. From what I understand from the spru234 document,
> the interrupt will be generated only at the end of all the transfers
> (i.e. all frames). There is an option to generate the interrupt at the
> end of each frame by configuring the ATCC bit.
> Probably the problem is due to the McASP... since it has an
> XBUF/RBUF of size only 32 bits???
The McASP should be telling the EDMA that it has a new word, and the EDMA
comes to get it. So the XBUF/RBUF will be cleared each time. But the EDMA
must be configured to be retreive a new word when the McBSP tells it that
there is a new one available. I think this is what needs to be done.
Robert
www.gldsp.com
--
No virus found in this outgoing message.
Checked by AVG Anti-Virus.
Version: 7.0.323 / Virus Database: 267.8.8/37 - Release Date: 7/1/2005
