Hello all,
I'm having a problem with the DSP failing to assert HOLDA after
seeing HOLD. I have a simple test program that writes 128
consecutive bytes (in 128 writes) to SDRAM. Occasionally, the DSP
will not give up the bus when requested. We assert HOLD after the DSP
has had the bus for 7.5uS. The problem only occurs after the code has
been optimized (-O3). It only occurs in writes to SDRAM. Here is our
system:
Dual 'C6701 DSPs running at 140MHz.
Summit 1553 interface chip.
CE0: 8MB of SDRAM
CE1: 4MB of flash
CE2: 2MB of SRAM, 1553 registers, FPGA registers.
CE3: FIFO read (2 1MB FIFOs).
We have an FPGA that arbitrates the bus between the two DSPs and the
1553. When the two DSPs are sharing the bus normally, each has the
bus for a 7.5uS timeslice. The 1553 has highest priority. The 1553
will attempt to transfer data for about 14uS. If it can't get the
bus, the transaction fails. This is what happens when the DSP holds
the bus for 10, 20, up to 80uS.
The DSP continues to do single writes to CE0 even though HOLD is
asserted. Has anyone seen this type of behavior? I read that the
'C62 had a problem missing HOLD if it coincided with an SDRAM refresh.
Thanks very much in advance.
-Jason
