Hi Clem,
yes, the problem is known! It also ras resulted in some grey hairs on my
head. I think it would save some time if TI had described the problem in the
PCI documentation a little bit better.
You have to invalidate L2Cache before reading data that was copied through
PCI Bus (or through EDMA). PCI copies using EDMA as far as I know. You read
cached data in your program. Your program doesnt know about the change in
external RAM.
You have to care about L2Cache coherency whenever you use EDMA to copy to or
from external RAM! There is a lot of documentation on that (check peripheral
reference manual for EDMA and L2Memory/Cache topics)
best regards,
thomas
----- Original Message -----
From: "Clem Taylor" <clem.taylor@clem...>
To: <c6x@c6x@...>
Sent: Saturday, August 06, 2005 7:27 AM
Subject: [c6x] DM642 PCI_xferTest() says the transfer is done, but it
isn't
really done...
> I'm using the PCI bus on the DM642 and
I've been having a rather
> annoying problem with PCI_xferTest() saying that a read DMA is done,
> but the data doesn't check correctly. However, if I check the data
a
> second time, it will be magically correct.
>
> It seems that even though PCI_xferTest() returns 0, the data hasn't
> actually made it to memory. So doing a read will return the old data,
> but doing another read a short time later will get the correct data.
> This problem doesn't happen that often and normally only on small
> transfers. I'm DMAing to SRAM, so it shouldn't be a cache
problem.
>
> 1) Issue PCI DMA on DM642 to copy from PCI address to SRAM:
> PCI_xfrConfigArgs ( ... )
> PCI_xfrStart ( PCI_READ_NOPREF );
> 2) Wait for DMA to compete:
> while ( PCI_xferTest() );
> 3) validate data in SRAM
> << sometimes this will fail if the transfer size is small (16-32
bytes) >>
> 4) validate data in SRAM again
> << this will pass >>
>
> Has anyone else had problems like this? I saw a problem like this on
> another processor, but in that case it turned out to be a silicon
> bug...
>
> Thanks,
> Clem
>
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Re: DM642 PCI xferTest() says the transfer is done, but it isn't really done...
Started by ●August 6, 2005
Reply by ●August 6, 20052005-08-06
On 8/6/05, krahvogl@krah... <krahvogl@krah...> wrote:
> You have to invalidate L2Cache before reading data that was copied through
> PCI Bus (or through EDMA). PCI copies using EDMA as far as I know. You read
> cached data in your program. Your program doesnt know about the change in
> external RAM.
We ran into the L2Cache problems and ended up moving all critical data
into the on chip memory. My current transfer problem is with the
buffer headers that are stored in the internal memory. So, I don't
think this is a L2 problem.
> You have to care about L2Cache coherency whenever you use EDMA to copy
> to or from external RAM! There is a lot of documentation on that (check
> peripheral reference manual for EDMA and L2Memory/Cache topics)
Yeah, I was amazed to find that the EDMA and external memory isn't
cache coherent. But it isn't surprising considering the external
memory controller isn't really integrated into the processor core, it
is just bolted on the side, just like the PCI controller.
Thanks,
Clem
> You have to invalidate L2Cache before reading data that was copied through
> PCI Bus (or through EDMA). PCI copies using EDMA as far as I know. You read
> cached data in your program. Your program doesnt know about the change in
> external RAM.
We ran into the L2Cache problems and ended up moving all critical data
into the on chip memory. My current transfer problem is with the
buffer headers that are stored in the internal memory. So, I don't
think this is a L2 problem.
> You have to care about L2Cache coherency whenever you use EDMA to copy
> to or from external RAM! There is a lot of documentation on that (check
> peripheral reference manual for EDMA and L2Memory/Cache topics)
Yeah, I was amazed to find that the EDMA and external memory isn't
cache coherent. But it isn't surprising considering the external
memory controller isn't really integrated into the processor core, it
is just bolted on the side, just like the PCI controller.
Thanks,
Clem
Reply by ●August 23, 20052005-08-23
