Hello,
I have a C6205 board with an external clock of 40 MHz. I have configured PLL_CFG
pins in order to get PLL work with frecuency 4 times greater. I use pull up,
pull down of value 22K. My surprise is that most of the times I dont get the
desired frecuency, I get a bigger one x10 or x6. Everything seem to be OK, RESET
witdth, configuration of pins. I have tried to toggle the reset pulse as
specified in Data sheet (giving two consecutive pulses),and sometimes it works
but not always. I need to give different Reset pulses in order to get it work
properly.
Any suggestion ?
Thanks
PLL problem on C6205
Started by ●September 5, 2005
Reply by ●September 8, 20052005-09-08
hi,
1) have you ensured that the rise time and fall time of the input 40MHz meet the dsp requirements?page 35 of the 6205 data sheet tells me that slew rate maximum is only 4ns.
2) As per page 9 of doc spra430a, there is an intrnal pull down of 30K for C64x devices. I am not sure whether this is applicable to C62x also. If yes, may be you need to try changing the pullup 22k to lower values.
3) page5 of the same doc tells about a series resistor 33K and recommended components. Have you followed these things also?
regards,
Dileepan.
1) have you ensured that the rise time and fall time of the input 40MHz meet the dsp requirements?page 35 of the 6205 data sheet tells me that slew rate maximum is only 4ns.
2) As per page 9 of doc spra430a, there is an intrnal pull down of 30K for C64x devices. I am not sure whether this is applicable to C62x also. If yes, may be you need to try changing the pullup 22k to lower values.
3) page5 of the same doc tells about a series resistor 33K and recommended components. Have you followed these things also?
regards,
Dileepan.
