DM642 - DSP/BIOS Interrupt Handling
DSP/BIOS or DM642 supports nested interrupts or not? I think it's not. While I
was examing CPU Interrupt Service Routines section of "Apps Using the
TMS320C6000 Enhanced DMA" application note, I have reached this result...
Because the doc says "Multiple EDMA channels can trigger the same interrupt,
it should be assumed that a new EDMA interrupt can occur in the time between
the CPU interrupt flag being cleared and the CIPR being read within the ISR"
... "if a new EDMA interrupt is received during that time, the CPU services it
without clearing the interrupt flag. This results in an additional CPU delay
caused by branching back to the main code body and immediately returning to
ISR for an interrrupt that has already been serviced." Also the example ISR
code takes consider this into and prevents this from happening by testing the
IFR status like
So basically if I understood it correctly two writes determine of IFR set
1) a new event completes, sets CIPR[L|H] and if the conditions are meet, sets
2) after clearing a CIPR bit[s], the logic in there bitwise-ANDs CIPR[L|H] and
CIER[L|H], and sets IFR as needed
Are my assumptations correct related to nested and IFR set conditions?
Thanks in advance...
daniel lusef <l...@yahoo.com> wrote:
Dear all,I attached C6711 block diagram and DSK C6711 block diagram. Actually i get this from book. But i want to know TI which document it describe .RegardsDaniel