I am trying to connect 2 32-bit sdram chip with emifa of dm642 for
that what the register values will be there for setting it.any one who try
plz give idea about it.and what is the setting or moderegister as i am
using CE0 for sdram connection.
Reply by Mike Dunn●September 13, 20052005-09-13
Ashish,
The settings are dependent on your physical design [trace length, bus
loading, etc.], your clock EMIF speed and the SDRAM vendor specifications.
Refer to TI document spra433d.pdf [there are also other docs on the web
site] to get an idea of what the settings mean and how to SDRAM specs to
determine the settings.
mikedunn
Ashish Valuskar <a...@gmail.com>
wrote:
Hello,
I am trying to connect 2 32-bit sdram chip with emifa of dm642 for
that what the register values will be there for setting it.any one who try
plz give idea about it.and what is the setting or moderegister as i am
using CE0 for sdram connection.
Reply by muth...@e-consystems.com●September 14, 20052005-09-14
Hello Asish,
In Externel memory interface,first u have to see the
1.clock of the SDRAM,regarding that u have to see the DM642
frequency.b'coz
the sdram may running at CLKIN/2 or CLKIN/4 or CLKIN.
This frequency selection depends on some register setting.
Ok i will list out the Register,which are u need set.
// GCTL - 0x01800000
// CE1 - 0x01800004
// CE0 - 0x01800008
// CE2 - 0x01800010
// CE3 - 0x01800014
// SDRAMCTL - 0x01800018
// SDRAMTIM - 0x0180001c
// SDRAMEXT - 0x01800020
// CE1ECCTL - 0x01800044
// CE0ECCTL - 0x01800048
// CE2ECCTL - 0x01800050
// CE3ECCTL - 0x01800054
depends on mapping u have to set CE0 or CE1 or CE2 or CE3
same as CCTL register also..
bye
muthu
Mike Dunn <mike-dunn@mike...> wrote:
> Ashish,
>
> The settings are dependent on your physical design [trace length, bus loading, > etc.], your clock EMIF speed and the SDRAM vendor
specifications.
>
> Refer to TI document spra433d.pdf [there are also other docs on the web site] > to get an idea of what the settings mean and how
to SDRAM specs to determine
> the settings.
>
> mikedunn
>
> Ashish Valuskar <ashvaluskar@ashv...> wrote:
> Hello,
> I am trying to connect 2 32-bit sdram chip with emifa of dm642 for that what > the register values will be there for setting
it.any one who try plz give
> idea about it.and what is the setting or moderegister as i am using CE0
for
> sdram connection.
>
>
> ---------------------------------
>
>
Reply by Mike Dunn●September 15, 20052005-09-15
Ashish,
After the device is reset [power on or otherwise], the L2 cache is disabled
and you should be able to access SDRAM after you init the EMIF.
If you can access on chip memory OK and you are having trouble getting the
SDRAM to work, you may want to try the following technique that I have used to
debug prototypes that may have assembly problems. [I am working a bit
blind here, since you did not specify what problem or symptom that you are
seeing.
Assuming that you have access to the SDRAM address and control pins, write
a simple program that accesses a single SDRAM location, does nothing for a few
cycles, and then loops. I use an asm program that writes the value that is
in a CPU register. Depending on your preference and tools, this can either
be a value that is manually changed in CCS, or automatically does a sliding bit
pattern on the address [0x80000004, 0x80000008, 0x80000010, etc]. Probe
the SDRAM address and control signals to see if you are getting the expected
results.
mikedunn
Ashish Valuskar <a...@gmail.com>
wrote:
hello mike,
thanks for suggestion and help.
one more thing i ant to know is there any L2 cache registers take part
while connecting with emifa and sdram.
On 9/13/05, Mike
Dunn <m...@sbcglobal.net> wrote:
Ashish,
The settings are dependent on your physical design [trace length, bus
loading, etc.], your clock EMIF speed and the SDRAM vendor specifications.
Refer to TI document spra433d.pdf [there are also other docs on the web
site] to get an idea of what the settings mean and how to SDRAM specs to
determine the settings.
mikedunn
Ashish Valuskar
<a...@gmail.com> wrote:
Hello,
I am trying to connect 2 32-bit sdram chip with emifa of dm642 for
that what the register values will be there for setting it.any one who try
plz give idea about it.and what is the setting or moderegister as i am
using CE0 for sdram connection.
