Hi All,
I am a newbie to this group. I have just started learning about DM642
and using the EVM board. I have few doubts that are raised from
reading the documents from TI regarding the Video ports.
Using Video port in raw-video mode, we would like to make 8-bit
transfer with SUM and DUM. The information coming in the video
port is like this...
'D' means Data
VP1 Data - D0,D2,D4,D6....(all 8-bit data)
VP2 Data - D1,D3,D5,D7....(all 8-bit data)
I need to move the data to SDRAM memory area in this manner..
D0,D1,D2,D3...
The technical document EDMA for 64-bit bus is not very clear. I am
writing up technical requirements. I am not able to find needed
information. This is all related to data transfer from a 64-bit
peripheral(video port fifo) to memory.
I have few questions that I have listed below. I would be grateful if
they can be answered.
1. Is it possible to make a transfer using EDMA, from Video FIFO
(64-bit bus), with element size as 8-bit? (TI document explains with
element size as 32-bit where one read -reads 64bits- and 2 write
cycles of 32bits each in consective memory location for transfering
the data from 64-bit bus. Is it possible to do the same with element
size as 8? -- This means that there will be one read -reads 64bits-
and 8 write cycles of 8bits each. )
2. If I make SUM as 00, DUM as 11 (Frame synchronised 1D to 1D
transfer), and element size as 8-bit, Can I make a transfer of the 8
bytes read (in one read) from 64-bit bus video fifo and transfer them
to 100Mhz SDRAM with offset between each 8-bit data?
I want to use a similar setup for VP2 and fill up these gaps.This is
supposed to write VP1 Data elemnts with certain gaps in between which
will be filled by VP2 Data using EDMA appropriately. Thereby, creating
an array of elements properly arranged as needed.
3. We can make transfers from 64-bit bus using element size as 32. the
document says that these data are transferred in 64-bit boundary and
will be stored in consecutive memory location. But does this mean,
when the data transfer is initiated from video fifo with SUM and
DUM, Indexing can be done at element size or is it possible only to
do the element indexing for every 64 bits (8 bytes) only.
Thanks
KT
DM642 and 64-bit bus transfer
Started by ●September 21, 2005
Reply by ●October 4, 20052005-10-04
Hi,
Sory for the late answer...
kumar_kt> I am a newbie to this group. I have just started learning about DM642
kumar_kt> and using the EVM board. I have few doubts that are raised from
kumar_kt> reading the documents from TI regarding the Video ports.
I am a newbie too so be prepared to check my suggestions, answers etc.
kumar_kt> Using Video port in raw-video mode, we would like to make 8-bit
kumar_kt> transfer with SUM and DUM. The information coming in the video
kumar_kt> port is like this...
kumar_kt> 'D' means Data
kumar_kt> VP1 Data - D0,D2,D4,D6....(all 8-bit data)
kumar_kt> VP2 Data - D1,D3,D5,D7....(all 8-bit data)
kumar_kt> I need to move the data to SDRAM memory area in this manner..
kumar_kt> D0,D1,D2,D3...
kumar_kt> The technical document EDMA for 64-bit bus is not very clear. I am
kumar_kt> writing up technical requirements. I am not able to find needed
kumar_kt> information. This is all related to data transfer from a 64-bit
kumar_kt> peripheral(video port fifo) to memory.
kumar_kt> I have few questions that I have listed below. I would be grateful if
kumar_kt> they can be answered.
kumar_kt> 1. Is it possible to make a transfer using EDMA, from Video FIFO
kumar_kt> (64-bit bus), with element size as 8-bit?
Yes, I think you can. Excerpt from the EDMA Ref. Guide, "The EDMACC can transfer
32-bit words, 16-bit half-words, or 8-bit bytes in a transfer. The EDMA
transfers have higher throughput when using 32-bit words; 16-bit and 8-bit
transfers always result in lower throughput.", and, "The addresses must be
aligned on the element size boundary. Word accesses must be aligned on a word
(multiple of 4) boundary and half-word accesses must be aligned on a half-word
(multiple of 2) boundary. Unaligned values will result in undefined operation"
But the problem is that one FIFO row must only contain one element. Because
if you use all 8 column, after reading one line how do you read the second
element in a row? So I think you have to put one element for each FIFO row.
Inefficient use of resources!
I think you may be two solutions to his. The first one and I think your best bet
for max. utilizing system resource is, if possible, to use L2 SRAM as a third
interface between VP and SDRAM. You can transfer VP data in bursts as 64 bits
and then you can decompose the data on much more speedier L2 SRAM. After doing
decompose you can write to SDRAM in burst mode as 32 bit quantities... According
to your load perhaps you can use an IDLE background function for it if you use
DSP/BIOS...
The second one may be doing it in SDRAM. You can write from VP FIFO to SDRAM in
64 bit quantities and do the decompose in there in the background. But this also
may lead to memory bottleneck...
There are some requirements using 64 bit peripherals on fixed mode. Excerpt from
EDMA Ref. Guide is below...
If the EDMA is setup with the following parameters:
- Element size is 32-bit word (ESIZE = 00b in OPTIONS field)
- Fixed-address mode on either source or destination (SUM or DUM = 00b in
OPTIONS field)
- Transfer/synchronization type is array/frame/block-synchronized (not
element-synchronized, see section 1.9.1)
- Element count is greater than 1 (ELECNT > 1)
- Either the source or destination bus width is 64 bits
Then you must ensure that the following conditions are true:
- Element count (ELECNT) must be a multiple of 2
- Frame/Array index field must be a multiple of 8 bytes (2 words, 1 doubleword)
- Both the source address and destination address must be doubleword aligned
(that is, a multiple of 8 bytes (2 words, 1 doubleword))
Operation is undefined, if the above conditions are not met.
kumar_ket> (TI document explains with element size as 32-bit where one read
kumar_ket> -reads 64bits- and 2 write cycles of 32bits each in consective memory
kumar_ket> location for transfering the data from 64-bit bus. Is it possible to
kumar_ket> do the same with element size as 8? -- This means that there will be
kumar_ket> one read -reads 64bits- and 8 write cycles of 8bits each. )
NO, you cant do it...
kumar_kt> 2. If I make SUM as 00, DUM as 11 (Frame synchronised 1D to 1D
kumar_kt> transfer), and element size as 8-bit, Can I make a transfer of the 8
kumar_kt> bytes read (in one read) from 64-bit bus video fifo and transfer them
kumar_kt> to 100Mhz SDRAM with offset between each 8-bit data?
NO. EIX(Element index) is only between elements not between bytes of an
element...
kumar_kt> 3. We can make transfers from 64-bit bus using element size as 32. the
kumar_kt> document says that these data are transferred in 64-bit boundary and
kumar_kt> will be stored in consecutive memory location. But does this mean,
kumar_kt> when the data transfer is initiated from video fifo with SUM and
kumar_kt> DUM, Indexing can be done at element size or is it possible only to
kumar_kt> do the element indexing for every 64 bits (8 bytes) only.
It depends on element size. If your element size is 32 bit, and want to transfer
64 bits in fact, you can do indexing at every 64 bit. If your element size is 8
bit, you can do indexing at 8 bits etc...
Dont forget bursting is only valid for consecutive locations either increment or
decrement. I dont know SDRAM details like what's the amount of transfer size in
bursting mode but If you are using indexed mode and even if you use 32 bit you
cant use bursting because you have gaps between these words...
--
Bora SAHIN
Sory for the late answer...
kumar_kt> I am a newbie to this group. I have just started learning about DM642
kumar_kt> and using the EVM board. I have few doubts that are raised from
kumar_kt> reading the documents from TI regarding the Video ports.
I am a newbie too so be prepared to check my suggestions, answers etc.
kumar_kt> Using Video port in raw-video mode, we would like to make 8-bit
kumar_kt> transfer with SUM and DUM. The information coming in the video
kumar_kt> port is like this...
kumar_kt> 'D' means Data
kumar_kt> VP1 Data - D0,D2,D4,D6....(all 8-bit data)
kumar_kt> VP2 Data - D1,D3,D5,D7....(all 8-bit data)
kumar_kt> I need to move the data to SDRAM memory area in this manner..
kumar_kt> D0,D1,D2,D3...
kumar_kt> The technical document EDMA for 64-bit bus is not very clear. I am
kumar_kt> writing up technical requirements. I am not able to find needed
kumar_kt> information. This is all related to data transfer from a 64-bit
kumar_kt> peripheral(video port fifo) to memory.
kumar_kt> I have few questions that I have listed below. I would be grateful if
kumar_kt> they can be answered.
kumar_kt> 1. Is it possible to make a transfer using EDMA, from Video FIFO
kumar_kt> (64-bit bus), with element size as 8-bit?
Yes, I think you can. Excerpt from the EDMA Ref. Guide, "The EDMACC can transfer
32-bit words, 16-bit half-words, or 8-bit bytes in a transfer. The EDMA
transfers have higher throughput when using 32-bit words; 16-bit and 8-bit
transfers always result in lower throughput.", and, "The addresses must be
aligned on the element size boundary. Word accesses must be aligned on a word
(multiple of 4) boundary and half-word accesses must be aligned on a half-word
(multiple of 2) boundary. Unaligned values will result in undefined operation"
But the problem is that one FIFO row must only contain one element. Because
if you use all 8 column, after reading one line how do you read the second
element in a row? So I think you have to put one element for each FIFO row.
Inefficient use of resources!
I think you may be two solutions to his. The first one and I think your best bet
for max. utilizing system resource is, if possible, to use L2 SRAM as a third
interface between VP and SDRAM. You can transfer VP data in bursts as 64 bits
and then you can decompose the data on much more speedier L2 SRAM. After doing
decompose you can write to SDRAM in burst mode as 32 bit quantities... According
to your load perhaps you can use an IDLE background function for it if you use
DSP/BIOS...
The second one may be doing it in SDRAM. You can write from VP FIFO to SDRAM in
64 bit quantities and do the decompose in there in the background. But this also
may lead to memory bottleneck...
There are some requirements using 64 bit peripherals on fixed mode. Excerpt from
EDMA Ref. Guide is below...
If the EDMA is setup with the following parameters:
- Element size is 32-bit word (ESIZE = 00b in OPTIONS field)
- Fixed-address mode on either source or destination (SUM or DUM = 00b in
OPTIONS field)
- Transfer/synchronization type is array/frame/block-synchronized (not
element-synchronized, see section 1.9.1)
- Element count is greater than 1 (ELECNT > 1)
- Either the source or destination bus width is 64 bits
Then you must ensure that the following conditions are true:
- Element count (ELECNT) must be a multiple of 2
- Frame/Array index field must be a multiple of 8 bytes (2 words, 1 doubleword)
- Both the source address and destination address must be doubleword aligned
(that is, a multiple of 8 bytes (2 words, 1 doubleword))
Operation is undefined, if the above conditions are not met.
kumar_ket> (TI document explains with element size as 32-bit where one read
kumar_ket> -reads 64bits- and 2 write cycles of 32bits each in consective memory
kumar_ket> location for transfering the data from 64-bit bus. Is it possible to
kumar_ket> do the same with element size as 8? -- This means that there will be
kumar_ket> one read -reads 64bits- and 8 write cycles of 8bits each. )
NO, you cant do it...
kumar_kt> 2. If I make SUM as 00, DUM as 11 (Frame synchronised 1D to 1D
kumar_kt> transfer), and element size as 8-bit, Can I make a transfer of the 8
kumar_kt> bytes read (in one read) from 64-bit bus video fifo and transfer them
kumar_kt> to 100Mhz SDRAM with offset between each 8-bit data?
NO. EIX(Element index) is only between elements not between bytes of an
element...
kumar_kt> 3. We can make transfers from 64-bit bus using element size as 32. the
kumar_kt> document says that these data are transferred in 64-bit boundary and
kumar_kt> will be stored in consecutive memory location. But does this mean,
kumar_kt> when the data transfer is initiated from video fifo with SUM and
kumar_kt> DUM, Indexing can be done at element size or is it possible only to
kumar_kt> do the element indexing for every 64 bits (8 bytes) only.
It depends on element size. If your element size is 32 bit, and want to transfer
64 bits in fact, you can do indexing at every 64 bit. If your element size is 8
bit, you can do indexing at 8 bits etc...
Dont forget bursting is only valid for consecutive locations either increment or
decrement. I dont know SDRAM details like what's the amount of transfer size in
bursting mode but If you are using indexed mode and even if you use 32 bit you
cant use bursting because you have gaps between these words...
--
Bora SAHIN
Reply by ●October 5, 20052005-10-05
Hi,
Thanks you very much for these clarifications. They were a great help
to me.
I had also sent this to TI. They had brought the
documents "SPRA994.pdf" and "SPRAA02.pdf" to my notice.
The document "SPRAA02.pdf" clearly states
"To make full utilization of bandwidth in the transfer engine, it is
important to fully utilize the bus width available and allow for data
bursting. It is best to use 32-bit element size whenever possible.
Setting element size in the options register (OPT) to 32 bits allows
a transfer to make full use of the available bus width, (whether it
is 32 or 64 bits wide) as well as allow the transfer to burst data in
multi-element blocks. Setting the element size to 16-bit or 8-bit
elements causes the EDMA to mask out the remaining data, wasting
bandwidth."
Thanks
KT
--- In c6x@c6x@..., Bora Sahin <bora.sahin@t...> wrote:
> Hi,
>
> Sory for the late answer...
>
> kumar_kt> I am a newbie to this group. I have just started learning
about DM642
> kumar_kt> and using the EVM board. I have few doubts that are
raised from
> kumar_kt> reading the documents from TI regarding the Video ports.
>
> I am a newbie too so be prepared to check my suggestions, answers
etc.
>
> kumar_kt> Using Video port in raw-video mode, we would like to make
8-bit
> kumar_kt> transfer with SUM and DUM. The information coming
in the video
> kumar_kt> port is like this...
> kumar_kt> 'D' means Data
> kumar_kt> VP1 Data - D0,D2,D4,D6....(all 8-bit data)
> kumar_kt> VP2 Data - D1,D3,D5,D7....(all 8-bit data)
>
> kumar_kt> I need to move the data to SDRAM memory area in this
manner..
> kumar_kt> D0,D1,D2,D3...
>
> kumar_kt> The technical document EDMA for 64-bit bus is not very
clear. I am
> kumar_kt> writing up technical requirements. I am not able to find
needed
> kumar_kt> information. This is all related to data transfer from a
64-bit
> kumar_kt> peripheral(video port fifo) to memory.
>
> kumar_kt> I have few questions that I have listed below. I would be
grateful if
> kumar_kt> they can be answered.
>
> kumar_kt> 1. Is it possible to make a transfer using EDMA, from
Video FIFO
> kumar_kt> (64-bit bus), with element size as 8-bit?
>
> Yes, I think you can. Excerpt from the EDMA Ref. Guide, "The EDMACC
can transfer
> 32-bit words, 16-bit half-words, or 8-bit bytes in a transfer. The
EDMA
> transfers have higher throughput when using 32-bit words; 16-bit
and 8-bit
> transfers always result in lower throughput.", and, "The addresses
must be
> aligned on the element size boundary. Word accesses must be aligned
on a word
> (multiple of 4) boundary and half-word accesses must be aligned on
a half-word
> (multiple of 2) boundary. Unaligned values will result in undefined
operation"
>
> But the problem is that one FIFO row must only contain one element.
Because
> if you use all 8 column, after reading one line how do you read the
second
> element in a row? So I think you have to put one element for each
FIFO row.
> Inefficient use of resources!
>
> I think you may be two solutions to his. The first one and I think
your best bet
> for max. utilizing system resource is, if possible, to use L2 SRAM
as a third
> interface between VP and SDRAM. You can transfer VP data in bursts
as 64 bits
> and then you can decompose the data on much more speedier L2 SRAM.
After doing
> decompose you can write to SDRAM in burst mode as 32 bit
quantities... According
> to your load perhaps you can use an IDLE background function for it
if you use
> DSP/BIOS...
>
> The second one may be doing it in SDRAM. You can write from VP FIFO
to SDRAM in
> 64 bit quantities and do the decompose in there in the background.
But this also
> may lead to memory bottleneck...
>
> There are some requirements using 64 bit peripherals on fixed mode.
Excerpt from
> EDMA Ref. Guide is below...
>
> If the EDMA is setup with the following parameters:
> - Element size is 32-bit word (ESIZE = 00b in OPTIONS field)
> - Fixed-address mode on either source or destination (SUM or DUM =
00b in
> OPTIONS field)
> - Transfer/synchronization type is array/frame/block-synchronized
(not
> element-synchronized, see section 1.9.1)
> - Element count is greater than 1 (ELECNT > 1)
> - Either the source or destination bus width is 64 bits
>
> Then you must ensure that the following conditions are true:
> - Element count (ELECNT) must be a multiple of 2
> - Frame/Array index field must be a multiple of 8 bytes (2 words, 1
doubleword)
> - Both the source address and destination address must be
doubleword aligned
> (that is, a multiple of 8 bytes (2 words, 1 doubleword))
>
> Operation is undefined, if the above conditions are not met.
>
> kumar_ket> (TI document explains with element size as 32-bit where
one read
> kumar_ket> -reads 64bits- and 2 write cycles of 32bits each in
consective memory
> kumar_ket> location for transfering the data from 64-bit bus. Is it
possible to
> kumar_ket> do the same with element size as 8? -- This means that
there will be
> kumar_ket> one read -reads 64bits- and 8 write cycles of 8bits
each. )
>
> NO, you cant do it...
>
> kumar_kt> 2. If I make SUM as 00, DUM as 11 (Frame synchronised 1D
to 1D
> kumar_kt> transfer), and element size as 8-bit, Can I make a
transfer of the 8
> kumar_kt> bytes read (in one read) from 64-bit bus video fifo and
transfer them
> kumar_kt> to 100Mhz SDRAM with offset between each 8-bit data?
>
> NO. EIX(Element index) is only between elements not between bytes
of an
> element...
>
> kumar_kt> 3. We can make transfers from 64-bit bus using element
size as 32. the
> kumar_kt> document says that these data are transferred in 64-bit
boundary and
> kumar_kt> will be stored in consecutive memory location. But does
this mean,
> kumar_kt> when the data transfer is initiated from video fifo with
SUM and
> kumar_kt> DUM, Indexing can be done at element size or is it
possible only to
> kumar_kt> do the element indexing for every 64 bits (8 bytes) only.
>
> It depends on element size. If your element size is 32 bit, and
want to transfer
> 64 bits in fact, you can do indexing at every 64 bit. If your
element size is 8
> bit, you can do indexing at 8 bits etc...
>
> Dont forget bursting is only valid for consecutive locations either
increment or
> decrement. I dont know SDRAM details like what's the amount of
transfer size in
> bursting mode but If you are using indexed mode and even if you use
32 bit you
> cant use bursting because you have gaps between these words...
>
> --
> Bora SAHIN
Thanks you very much for these clarifications. They were a great help
to me.
I had also sent this to TI. They had brought the
documents "SPRA994.pdf" and "SPRAA02.pdf" to my notice.
The document "SPRAA02.pdf" clearly states
"To make full utilization of bandwidth in the transfer engine, it is
important to fully utilize the bus width available and allow for data
bursting. It is best to use 32-bit element size whenever possible.
Setting element size in the options register (OPT) to 32 bits allows
a transfer to make full use of the available bus width, (whether it
is 32 or 64 bits wide) as well as allow the transfer to burst data in
multi-element blocks. Setting the element size to 16-bit or 8-bit
elements causes the EDMA to mask out the remaining data, wasting
bandwidth."
Thanks
KT
--- In c6x@c6x@..., Bora Sahin <bora.sahin@t...> wrote:
> Hi,
>
> Sory for the late answer...
>
> kumar_kt> I am a newbie to this group. I have just started learning
about DM642
> kumar_kt> and using the EVM board. I have few doubts that are
raised from
> kumar_kt> reading the documents from TI regarding the Video ports.
>
> I am a newbie too so be prepared to check my suggestions, answers
etc.
>
> kumar_kt> Using Video port in raw-video mode, we would like to make
8-bit
> kumar_kt> transfer with SUM and DUM. The information coming
in the video
> kumar_kt> port is like this...
> kumar_kt> 'D' means Data
> kumar_kt> VP1 Data - D0,D2,D4,D6....(all 8-bit data)
> kumar_kt> VP2 Data - D1,D3,D5,D7....(all 8-bit data)
>
> kumar_kt> I need to move the data to SDRAM memory area in this
manner..
> kumar_kt> D0,D1,D2,D3...
>
> kumar_kt> The technical document EDMA for 64-bit bus is not very
clear. I am
> kumar_kt> writing up technical requirements. I am not able to find
needed
> kumar_kt> information. This is all related to data transfer from a
64-bit
> kumar_kt> peripheral(video port fifo) to memory.
>
> kumar_kt> I have few questions that I have listed below. I would be
grateful if
> kumar_kt> they can be answered.
>
> kumar_kt> 1. Is it possible to make a transfer using EDMA, from
Video FIFO
> kumar_kt> (64-bit bus), with element size as 8-bit?
>
> Yes, I think you can. Excerpt from the EDMA Ref. Guide, "The EDMACC
can transfer
> 32-bit words, 16-bit half-words, or 8-bit bytes in a transfer. The
EDMA
> transfers have higher throughput when using 32-bit words; 16-bit
and 8-bit
> transfers always result in lower throughput.", and, "The addresses
must be
> aligned on the element size boundary. Word accesses must be aligned
on a word
> (multiple of 4) boundary and half-word accesses must be aligned on
a half-word
> (multiple of 2) boundary. Unaligned values will result in undefined
operation"
>
> But the problem is that one FIFO row must only contain one element.
Because
> if you use all 8 column, after reading one line how do you read the
second
> element in a row? So I think you have to put one element for each
FIFO row.
> Inefficient use of resources!
>
> I think you may be two solutions to his. The first one and I think
your best bet
> for max. utilizing system resource is, if possible, to use L2 SRAM
as a third
> interface between VP and SDRAM. You can transfer VP data in bursts
as 64 bits
> and then you can decompose the data on much more speedier L2 SRAM.
After doing
> decompose you can write to SDRAM in burst mode as 32 bit
quantities... According
> to your load perhaps you can use an IDLE background function for it
if you use
> DSP/BIOS...
>
> The second one may be doing it in SDRAM. You can write from VP FIFO
to SDRAM in
> 64 bit quantities and do the decompose in there in the background.
But this also
> may lead to memory bottleneck...
>
> There are some requirements using 64 bit peripherals on fixed mode.
Excerpt from
> EDMA Ref. Guide is below...
>
> If the EDMA is setup with the following parameters:
> - Element size is 32-bit word (ESIZE = 00b in OPTIONS field)
> - Fixed-address mode on either source or destination (SUM or DUM =
00b in
> OPTIONS field)
> - Transfer/synchronization type is array/frame/block-synchronized
(not
> element-synchronized, see section 1.9.1)
> - Element count is greater than 1 (ELECNT > 1)
> - Either the source or destination bus width is 64 bits
>
> Then you must ensure that the following conditions are true:
> - Element count (ELECNT) must be a multiple of 2
> - Frame/Array index field must be a multiple of 8 bytes (2 words, 1
doubleword)
> - Both the source address and destination address must be
doubleword aligned
> (that is, a multiple of 8 bytes (2 words, 1 doubleword))
>
> Operation is undefined, if the above conditions are not met.
>
> kumar_ket> (TI document explains with element size as 32-bit where
one read
> kumar_ket> -reads 64bits- and 2 write cycles of 32bits each in
consective memory
> kumar_ket> location for transfering the data from 64-bit bus. Is it
possible to
> kumar_ket> do the same with element size as 8? -- This means that
there will be
> kumar_ket> one read -reads 64bits- and 8 write cycles of 8bits
each. )
>
> NO, you cant do it...
>
> kumar_kt> 2. If I make SUM as 00, DUM as 11 (Frame synchronised 1D
to 1D
> kumar_kt> transfer), and element size as 8-bit, Can I make a
transfer of the 8
> kumar_kt> bytes read (in one read) from 64-bit bus video fifo and
transfer them
> kumar_kt> to 100Mhz SDRAM with offset between each 8-bit data?
>
> NO. EIX(Element index) is only between elements not between bytes
of an
> element...
>
> kumar_kt> 3. We can make transfers from 64-bit bus using element
size as 32. the
> kumar_kt> document says that these data are transferred in 64-bit
boundary and
> kumar_kt> will be stored in consecutive memory location. But does
this mean,
> kumar_kt> when the data transfer is initiated from video fifo with
SUM and
> kumar_kt> DUM, Indexing can be done at element size or is it
possible only to
> kumar_kt> do the element indexing for every 64 bits (8 bytes) only.
>
> It depends on element size. If your element size is 32 bit, and
want to transfer
> 64 bits in fact, you can do indexing at every 64 bit. If your
element size is 8
> bit, you can do indexing at 8 bits etc...
>
> Dont forget bursting is only valid for consecutive locations either
increment or
> decrement. I dont know SDRAM details like what's the amount of
transfer size in
> bursting mode but If you are using indexed mode and even if you use
32 bit you
> cant use bursting because you have gaps between these words...
>
> --
> Bora SAHIN
