The TMS320C6205GHK200 data sheet (SPRS106E) shows a 3ns minimum hold
requirement for the EDx during DSP reads from SDRAM.
The 100 to 143 MHz SDRAMs that I have been able to find have data hold time
specifications of 2.5ns. This results in a -500ps data hold margin on DSP SDRAM
reads. Faster grade (higher spec.) SDRAMs have even lower data hold
specifications making this particular problem even worse.
The setup margin for DSP writes to SDRAM is also 0ns for the combination
of these two devices. That seems a little tight considering the EMIF clock
jitter specification. Going to the next faster speed grade would give 500ps of
setup margin, but would now result in a -1ns data hold margin (yikes!) on DSP
data writes to SDRAM.
Does anyone have any guidance on selecting SDRAM parts to work with the
'C6205 EMIF?
Joe
