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Re: U18 PAL contents for DSK6711
Hope this helps:
MODULE U18_PALB
TITLE '
PAL NAME: PAL_B
PAL #: U18,
980*
DWG NAME: TMS320C6711 DSP Starter Kit
(DSK)
ASSY #: D600980-0001*
COMPANY: Texas Instruments
Incorporated
SYNTHESIS TOOL: Synario Project Navigator version
4.10'
U18 device 'P22V10C'; "The
PALLV22V10 is a 28-pin PLCC
"DESCRIPTION
"This module controls the C6711
DSK resets, I/O port reads/writes,
"and daughterboard buffers
direction & output signals.
"Inputs
ECLK pin 2; "DSP EMIF
CLocK (AKA, ECLKOUT in other docs.)
PPC_TBC_RST_ pin 3;
"PPC's Test Bus Controller ReSeT
EA19 pin 4; "Splits
CE1 space in two
"Low = Flash ROM address space
"High = I/O port address space
SVS_RST_
pin 5; "Supply Voltage Supervisor ReSeT
PPC_DSP_RST_ pin 6;
"PPC's Digital Signal Processor ReSeT
PBSW_RST_ pin
7; "Push Button SWitch ReSeT
CE1_ pin 9; "Chip
Enable 1 from the DSP's EMIF
CE2_ pin 10; "Chip Enable 2
from the DSP's EMIF
CE3_ pin 11; "Chip Enable 3
from the DSP's EMIF
AOE_ pin 12; "Asynchronous
Output Enable from the DSP's EMIF
"Shown as SDRAS_/AOE_ in the schematics
ARE_ pin 13; "Asynchronous
Read Enable from the DSP's EMIF
"Shown as SDCAS_/ARE_ in the schematics3
AWE_ pin 16; "Asynchronous
Write Enable from the DSP's EMIF
"Shown as SDWE_/AWE_ in the schematics
"Outputs
DSK_RST_ pin
17; "DSK board-level ReSeT
TBC_RST_ pin
18; "Test Bus Controller ReSeT
PPC_RST_ pin
19; "MANual ReSeT to voltage supervisor
DSP_RST_ pin
20; "Digital Signal Processor ReSeT (active low)
CE1_ROM_ pin
21; "CE1 Read-Only Memory chip enable
RD_IOPORT_ pin 23;
"ReaD the I/O PORT (direction signal)
WR_IOPORT pin 24;
"WRite the I/O PORT (direction signal)
DB_OE_ pin 25; "DaughterBoard Output
Enable
DB_DIR pin 26; "DaughterBoard
DIRection
TP22 pin 27; "Test Point
(unused I/O pin)
"Constants
h,l,x = 1, 0, .X. ;
EQUATIONS
"------------------------------
"DSK ReSeT
!DSK_RST_ = !SVS_RST_ #
!PBSW_RST_;
"TBC ReSeT
!TBC_RST_ = !PPC_TBC_RST_ #
!SVS_RST_;
"Parallel Port Controller
ReSeT
!PPC_RST_ = !SVS_RST_;
"DSP ReSeT
!DSP_RST_ = !PPC_DSP_RST_ # !SVS_RST_ #
!PBSW_RST_;
"------------------------------
"I/O port reads/writes are done by
decoding the DSP's EMIF address
"line EA19. The DSP's
CE1 (chip enable space 1) address space is
"divided into two by decoding
EA19; the lower half addresses the
"Flash ROM and the upper half
addresses the I/O port ('374 device).
"Other logic determines the I/O
port mode as either read or write.
"Enables the ROM in CE1 space
!CE1_ROM_ = !CE1_ & !EA19;
"ReaD the I/O PORT
!RD_IOPORT_ = !CE1_ & EA19
& !ARE_;
"WRite the I/O PORT
WR_IOPORT = !CE1_
& EA19 & !AWE_;
"------------------------------
"Daughterboard buffers direction
and output logic determines
"whether daughterboard buffers are
output enabled. It also
"determines whether the buffers
are in read (daughterboard to DSK)
"or write (DSK to daughterboard)
mode.
"DaughterBoard Output Enable
"Low = output to
DB enabled
"High = output to DB
disabled
DB_OE_ = 0;
"DaughterBoard DIRection
"Low = write
DaughterBoard data bus
"High = read
DaughtetBoard data bus
DB_DIR = !(AOE_ # (CE2_
& CE3_));
"Test Point (unused I/O
pin(s))
TP22 = 0;
TP22.OE= 0;
"====================================================================
" NOTE:
" The format of the vectors is as
follows:
"[
Inputs ] ->
[ Outputs ];
"====================================================================
"Test Point(s) (unused I/O pin(s))
aren't tested because their "inputs are tied low
(non-variable inputs) TEST_VECTORS
([ SVS_RST_, PBSW_RST_ ] -> DSK_RST_)
[
0,
0 ] -> 0;
[
0,
1 ] -> 0;
[
1,
0 ] -> 0;
[
1,
1 ] -> 1;
TEST_VECTORS
([ PPC_TBC_RST_, SVS_RST_ ] -> TBC_RST_
)
[
0,
0 ] -> 0;
[
0,
1 ] -> 0;
[
1,
0 ] -> 0;
[
1,
1 ] -> 1;
TEST_VECTORS
([ SVS_RST_ ] -> PPC_RST_ )
[
0 ] -> 0;
[
1 ] -> 1;
TEST_VECTORS
([ PPC_DSP_RST_, SVS_RST_, PBSW_RST_ ] ->
DSP_RST_ )
[
0,
0,
0 ] -> 0;
[
0,
0,
1 ] -> 0;
[
0,
1,
0 ] -> 0;
[
0,
1,
1 ] -> 0;
[
1,
0,
0 ] -> 0;
[
1,
0,
1 ] -> 0;
[
1,
1,
0 ] -> 0;
[
1,
1,
1 ] -> 1;
TEST_VECTORS
([ CE1_, EA19 ] -> CE1_ROM_ )
[ 0,
0 ] -> 0;
[ 0,
1 ] -> 1;
[ 1,
0 ] -> 1;
[ 1,
1 ] -> 1;
TEST_VECTORS
([ CE1_, EA19, ARE_ ] -> RD_IOPORT_
)
[ 0,
0, 0 ] -> 1;
[ 0,
0, 1 ] -> 1;
[ 0,
1, 0 ] -> 0;
[ 0,
1, 1 ] -> 1;
[ 1,
0, 0 ] -> 1;
[ 1,
0, 1 ] -> 1;
[ 1,
1, 0 ] -> 1;
[ 1,
1, 1 ] -> 1;
TEST_VECTORS
([ CE1_, EA19, AWE_ ] -> WR_IOPORT )
[ 0,
0, 0 ] -> 0;
[ 0,
0, 1 ] -> 0;
[ 0,
1, 0 ] -> 1;
[ 0,
1, 1 ] -> 0;
[ 1,
0, 0 ] -> 0;
[ 1,
0, 1 ] -> 0;
[ 1,
1, 0 ] -> 0;
[ 1,
1, 1 ] -> 0;
TEST_VECTORS
([ CE2_, CE3_ ] -> DB_OE_ )
[ 0,
0] -> 1;
[ 0,
1] -> 0;
[ 1,
0] -> 0;
[ 1,
1] -> 1;
TEST_VECTORS
([ AOE_ ] -> DB_DIR )
[ 0 ] -> 1;
[ 1 ] -> 0;
END
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