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FW: U20 PAL contents for DSK6711
Hope this helps:
MODULE U20_PALA
TITLE '
PAL NAME: PAL_A
PAL #: U20, 980*
DWG NAME: TMS320C6711 DSP Starter Kit (DSK)
ASSY #: D600980-0001*
COMPANY: Texas Instruments Incorporated
SYNTHESIS TOOL: Synario Project Navigator version
4.10'
U20 device 'P22V10C'; "The PALLV22V10 is
a 28-pin PLCC
"DESCRIPTION
"This module controls the C6711 DSK boot mode
(C6711), generates
"TBC read and write signals, and controls the
parallel port buffer
"direction.
"Inputs
PPC_BCLK pin 2; "Parallel Port
Controller(PPC) Bus CLocK
RST_HD8 pin 3; "ReSeT value
on Host Data bit 8(HD8) - endianess
RST_HD4 pin 4; "ReSeT value
on HD4 - C6711 boot mode MS-bit
RST_HD3 pin 5; "ReSeT value
on HD3 - C6711 boot mode LS-bit
PPC_SWR_ pin 6; "PPC System
WRite
PPC_SRD_ pin 7; "PPC System
ReaD
TBC_CS_ pin 9; "Test Bus
Controller(TBC) Chip Select(from PPC)
TBC_RDY_ pin 10; "TBC ReaDY(from
TBC)
TBC_INT_ pin 11; "TBC INTerrupt(from
TBC)
HINIT_ pin 12; "Host
INiTiate(from PPC)
HSTB_ pin 13; "Host
STroBe(from PPC)
EPP_SPP_ pin 16; "EPP/SPP mode
detect(from PPC)
DSP_RST_ pin 27; "Digital Signal
Processor ReSeT
"Outputs
TP4 pin 17
;"Test Point (unused I/O pin)
TP5 pin 18
;"Test Point (unused I/O pin)
TP6 pin 19
;"Test Point (unused I/O pin)
TBC_WR_ pin 20 ; "TBC WRite
TBC_RD_ pin 21 istype 'reg_D';
"TBC ReaD
PP_R_W_ pin 23 istype
'com'; "Parallel Port direction control
HD8 pin 24
;"HPI Data bit 8 determines endianess at reset
HD4 pin 25
;"HPI D4 used with D3 to determine boot mode
HD3 pin 26
;"HPI D3 used with D4 to determine boot mode
"Constants
h,l,x,z,c = 1, 0, .X., .Z., .C.;
EQUATIONS
"------------------------------
"Test Point(s) (unused I/O pin(s))
TP4 = 0;
TP4.OE= 0;
TP5 = 0;
TP5.OE= 0;
TP6 = 0;
TP6.OE= 0;
"------------------------------
"TBC ReaD timing needs a lengthened PPC System
ReaD signal.
TBC_RD_.clk = PPC_BCLK;
!TBC_RD_.D = !PPC_SRD_ &
!TBC_CS_;
"TBC WRite.
!TBC_WR_ = !PPC_SWR_ &
!TBC_CS_;
"------------------------------
"Different parallel port signals determine the
direction of data
"flow for the bidirectional signals in Standard
(SPP) and Enhanced
"Parallel Port (EPP) modes of operation:
" Mode Direction
signal RD WR
" SPP
nINIT
0 1
" EPP
nSTB
1 0
TRUTH_TABLE
([EPP_SPP_, HINIT_, HSTB_] -> PP_R_W_ )
[0, x,
1 ] -> 1; "EPP mode host read from
PPC
[0, x,
0 ] -> 0; "EPP mode host write to
PPC
[1, 1,
x ] -> 0; "SPP mode host write to
PPC
[1, 0,
x ] -> 1; "SPP mode host read from
PPC
EQUATIONS
"------------------------------
"The endianess and boot mode of the C6711 DSP
on the DSK are
"determined by the values found on host data
bits during reset.
"An output enable is required for each bit to stop
driving the
"value onto (tri-state) the PPC data bus after
reset.
HD8 = RST_HD8;
HD8.OE = !DSP_RST_;
HD4 = RST_HD4;
HD4.OE = !DSP_RST_;
HD3 = RST_HD3;
HD3.OE = !DSP_RST_;
"====================================================================
" NOTE:
" The format of the vectors is as follows:
"[
Inputs ] ->
[ Outputs ];
"====================================================================
"Test Point(s) (unused I/O pin(s)) aren't
tested because their
"inputs are tied low (non-variable
inputs)
TEST_VECTORS
([ PPC_BCLK, TBC_CS_, PPC_SWR_, PPC_SRD_ ] -> [ TBC_WR_,
TBC_RD_ ])
[ c,
0,
0, 0
] -> [
0, 0 ];
[ c,
0,
0, 1
] -> [
0, 1 ];
[ c,
0,
1, 0
] -> [
1, 0 ];
[ c,
0,
1, 1
] -> [
1, 1 ];
[ c,
1,
0, 0
] -> [
1, 1 ];
[ c,
1,
0, 1
] -> [
1, 1 ];
[ c,
1,
1, 0
] -> [
1, 1 ];
[ c,
1,
1, 1
] -> [
1, 1 ];
TEST_VECTORS
([ EPP_SPP_, HINIT_, HSTB_ ] -> PP_R_W_ )
"[ 0,
0, 0 ] -> 1;
[ 0,
0, 1 ] -> 1;
[ 0,
1, 0 ] -> 0;
"[ 0,
1, 1 ] -> 0;
"[ 1,
0, 0 ] -> 0;
[ 1,
0, 1 ] -> 1;
[ 1,
1, 0 ] -> 0;
"[ 1,
1, 1 ] -> 1;
TEST_VECTORS
([ DSP_RST_, RST_HD8, RST_HD4, RST_HD3 ] ->
[ HD8, HD4, HD3 ])
[ 0,
0, 0,
0 ] -> [ 0,
0, 0 ];
[ 0,
0, 0,
1 ] -> [ 0,
0, 1 ];
[ 0,
0, 1,
0 ] -> [ 0,
1, 0 ];
[ 0,
0, 1,
1 ] -> [ 0,
1, 1 ];
[ 0,
1, 0,
0 ] -> [ 1,
0, 0 ];
[ 0,
1, 0,
1 ] -> [ 1,
0, 1 ];
[ 0,
1, 1,
0 ] -> [ 1,
1, 0 ];
[ 0,
1, 1,
1 ] -> [ 1,
1, 1 ];
[ 1,
0, 0,
0 ] -> [ z,
z, z ];
[ 1,
0, 0,
1 ] -> [ z,
z, z ];
[ 1,
0, 1,
0 ] -> [ z,
z, z ];
[ 1,
0, 1,
1 ] -> [ z,
z, z ];
[ 1,
1, 0,
0 ] -> [ z,
z, z ];
[ 1,
1, 0,
1 ] -> [ z,
z, z ];
[ 1,
1, 1,
0 ] -> [ z,
z, z ];
[ 1,
1, 1,
1 ] -> [ z,
z, z ];
END
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