Hi
I'm working on the implementation of a TDM driver with 6416 processor.
The McBSP is used to transfer data through EDMA. The clock for McBSP is
provided by an external device. Due to some lack in synchronisation
between McBSP and EDMA, the data appears shifted and appears in the next
channel. The data for channel 0 is in channel 1, data for channel 1 is
in channel 2 and so on.
A document by TI, TMS320C6000 DSP Multichannel Buffered Serial Port
(McBSP) Reference Guide (SPRU580E) section 7.2 specifically addresses
this problem. I followed the initialization procedure as specified in
it. But the system still behaves in the same way. I've attached the
McBSP initialization code and the ISR along with the document SPRU 580E.
If somebody can point out where I'm going wrong, that would be most
helpful.
regards
Ramkumar
static void StartMcBSP(){
// Program serial channel McBSP0
Mc0(SPCR) = 0x00000000; // Reset SPCR
Mc0(PCR) = 0x0000; //PCR_SS; // Pin polarity setup ( not
inverted on 64xx )
Mc0(RCR) = 0x00041F00; // 32 channels; 8 bit elements; Data Delay = 0
Mc0(XCR) = 0x00001F00; // 32 channels; 8 bit elements; Data Delay = 0
Mc0(MCR) = 0x00030001; // Use RCER for determining the open channels
Mc0(RCER0) = 0xFFFFFFFF; // Enable all channels
Mc0(XCER0) = 0xFFFFFFFF;
Mc0(SRGR) = SRGR_SS; // Sample rate generator is not used
Mc0(SPCR) = 0x00200000; // Set XINTM to 2h
{ int i;
for( i = 0; i < 0x1000; i++ ); // That takes more than 1 microsecond
}
Mc0(SPCR) |= 0x00010000; // Enable XRST
#if 0
{ int i;
for( i = 0; i < 0x1000; i++ ); // That takes more than 1 microsecond
}
#endif
while(!(Mc0(SPCR)&(1<<19))); // Wait till XSYNCERR occurs
Mc0(SPCR) &= 0xFFFEFFFF; // Disable XRST after that
initdma(rxcur,rxnext,txcur,txnext); //Initialize EDMA here
ICR = XINT0 ; // Clear any residual interrupt flags
IER |= XINT0; // Enable XINT for McBSP
return;
}
/* This is the ISR to service McBSP XINT */
void c_int07( void )
{
Mc0(SPCR) &= 0xFFCFFFFF; // Set XINTM to 0h
ICR = XINT0; // Clear any residual interrupt flags
IER &= ~XINT0; // Disable XINT
Mc0(XCR) |= 1<<18;
Mc0(SPCR) |= 0x00010001; // Enable XRST and RRST
}
