All,
Has anyone else come across problems using spread spectrum clock
generator (SSCG) chips for EMI reduction ?
We use a C6713 that gets its clock from a Cypress CY25811 SSCG that is
used for EMI reduction. The problem is that our code crashes after
2-40 hours with the SSCG in place. If we disable the spread spectrum
feature of the same chip everything seems to run fine.
Are there any known issues when using SSCGs with DSPs ?
- Andrew E.
C6713 and spread spectrum clock generator
Started by ●August 7, 2006
Reply by ●August 8, 20062006-08-08
Jeff,
Deviation is +/- 1.2 %.
Modulation waveform looks like a rounded off triangle wave.
/\/\/\/\/\/\ type thing.
Modulation period is 47 kHz, which corresponds to a period of ~20 usec.
Just heard back from TI support that they don't have a spec. for
acceptable clock jitter. Problem is that we need SSCG to reduce EMI for FCC.
Weird thing is that we have been using TI DSPs for some 10+ years and
haven't run in to this before.
- Andrew
Jeff Brower wrote:
>Andrew-
>
>
>
>>Has anyone else come across problems using spread spectrum clock
>>generator (SSCG) chips for EMI reduction ?
>>
>>We use a C6713 that gets its clock from a Cypress CY25811 SSCG that is
>>used for EMI reduction. The problem is that our code crashes after
>>2-40 hours with the SSCG in place. If we disable the spread spectrum
>>feature of the same chip everything seems to run fine.
>>
>>Are there any known issues when using SSCGs with DSPs ?
>>
>>TI DSPs are sensitive to clock jitter, always have been. What is your maximum
>frequency % deviation? What is the modulation waveform and period?
>
>-Jeff
>
>
>
Deviation is +/- 1.2 %.
Modulation waveform looks like a rounded off triangle wave.
/\/\/\/\/\/\ type thing.
Modulation period is 47 kHz, which corresponds to a period of ~20 usec.
Just heard back from TI support that they don't have a spec. for
acceptable clock jitter. Problem is that we need SSCG to reduce EMI for FCC.
Weird thing is that we have been using TI DSPs for some 10+ years and
haven't run in to this before.
- Andrew
Jeff Brower wrote:
>Andrew-
>
>
>
>>Has anyone else come across problems using spread spectrum clock
>>generator (SSCG) chips for EMI reduction ?
>>
>>We use a C6713 that gets its clock from a Cypress CY25811 SSCG that is
>>used for EMI reduction. The problem is that our code crashes after
>>2-40 hours with the SSCG in place. If we disable the spread spectrum
>>feature of the same chip everything seems to run fine.
>>
>>Are there any known issues when using SSCGs with DSPs ?
>>
>>TI DSPs are sensitive to clock jitter, always have been. What is your maximum
>frequency % deviation? What is the modulation waveform and period?
>
>-Jeff
>
>
>
Reply by ●August 8, 20062006-08-08
Andrew-
> Has anyone else come across problems using spread spectrum clock
> generator (SSCG) chips for EMI reduction ?
>
> We use a C6713 that gets its clock from a Cypress CY25811 SSCG that is
> used for EMI reduction. The problem is that our code crashes after
> 2-40 hours with the SSCG in place. If we disable the spread spectrum
> feature of the same chip everything seems to run fine.
>
> Are there any known issues when using SSCGs with DSPs ?
TI DSPs are sensitive to clock jitter, always have been. What is your maximum
frequency % deviation? What is the modulation waveform and period?
-Jeff
> Has anyone else come across problems using spread spectrum clock
> generator (SSCG) chips for EMI reduction ?
>
> We use a C6713 that gets its clock from a Cypress CY25811 SSCG that is
> used for EMI reduction. The problem is that our code crashes after
> 2-40 hours with the SSCG in place. If we disable the spread spectrum
> feature of the same chip everything seems to run fine.
>
> Are there any known issues when using SSCGs with DSPs ?
TI DSPs are sensitive to clock jitter, always have been. What is your maximum
frequency % deviation? What is the modulation waveform and period?
-Jeff
Reply by ●August 22, 20062006-08-22
Hi Jeff,
Did try smaller spread spectrum deviation - to no affect.
The chip we are using doesn't allow us to reduce the period.
Yes, it did used to work with the 6713. The other variable that I didn't
mention is that we use a PCI2040 to communicate with the 6713 via its
HPI interface. The PCI2040 provides a slave PCI interface. It turns out
that the failure is dependant on the PC we put the card in as well. It
is as if certain newer PCs cause HPI transaction sequences that somehow
interact with the effects the SSCG has on the 6713. All complicated and
difficult to pin down.
For the moment we have disabled the SSCG and will be retesting EMI.
Maybe there are some other options for reducing EMI.
Thanks for the comments and suggestions !
- Andrew E.
Jeff Brower wrote:
> Andrew-
>
>> Deviation is +/- 1.2 %.
>> Modulation waveform looks like a rounded off triangle wave.
>> /\/\/\/\/\/\ type thing.
>> Modulation period is 47 kHz, which corresponds to a period of ~20 usec.
> This doesn't seem that aggressive. I'm sure you tried less deviation
> and longer period -- did that achieve reliability?
>
>> Just heard back from TI support that they don't have a spec. for
>> acceptable clock jitter. Problem is that we need SSCG to reduce EMI
>> for FCC.
>>
>> Weird thing is that we have been using TI DSPs for some 10+ years and
>> haven't run in to this before.
>> Did it used to work with 6713? Any changes -- faster clock rate,
> differnt PLL multiplier, new silicon revision? Maybe it's just
> borderline, and you added more code, more DMA channels, etc (more
> overall 'demand' on the chip) so the chip runs slightly hotter, just
> enough to put it over the edge on jitter sensitivity. What happens if
> you provide cooling (fan) on the chip?
>
> -Jeff
>
>> Jeff Brower wrote:
>>
>>>Andrew-
>>>
>>>
>>>
>>>>Has anyone else come across problems using spread spectrum clock
>>>>generator (SSCG) chips for EMI reduction ?
>>>>
>>>>We use a C6713 that gets its clock from a Cypress CY25811 SSCG that is
>>>>used for EMI reduction. The problem is that our code crashes after
>>>>2-40 hours with the SSCG in place. If we disable the spread spectrum
>>>>feature of the same chip everything seems to run fine.
>>>>
>>>>Are there any known issues when using SSCGs with DSPs ?
>>>>
>>>>
>>>
>>> TI DSPs are sensitive to clock jitter, always have been. What is
>>> your maximum
>>> frequency % deviation? What is the modulation waveform and period?
>>>
>>> -Jeff
>>
Did try smaller spread spectrum deviation - to no affect.
The chip we are using doesn't allow us to reduce the period.
Yes, it did used to work with the 6713. The other variable that I didn't
mention is that we use a PCI2040 to communicate with the 6713 via its
HPI interface. The PCI2040 provides a slave PCI interface. It turns out
that the failure is dependant on the PC we put the card in as well. It
is as if certain newer PCs cause HPI transaction sequences that somehow
interact with the effects the SSCG has on the 6713. All complicated and
difficult to pin down.
For the moment we have disabled the SSCG and will be retesting EMI.
Maybe there are some other options for reducing EMI.
Thanks for the comments and suggestions !
- Andrew E.
Jeff Brower wrote:
> Andrew-
>
>> Deviation is +/- 1.2 %.
>> Modulation waveform looks like a rounded off triangle wave.
>> /\/\/\/\/\/\ type thing.
>> Modulation period is 47 kHz, which corresponds to a period of ~20 usec.
> This doesn't seem that aggressive. I'm sure you tried less deviation
> and longer period -- did that achieve reliability?
>
>> Just heard back from TI support that they don't have a spec. for
>> acceptable clock jitter. Problem is that we need SSCG to reduce EMI
>> for FCC.
>>
>> Weird thing is that we have been using TI DSPs for some 10+ years and
>> haven't run in to this before.
>> Did it used to work with 6713? Any changes -- faster clock rate,
> differnt PLL multiplier, new silicon revision? Maybe it's just
> borderline, and you added more code, more DMA channels, etc (more
> overall 'demand' on the chip) so the chip runs slightly hotter, just
> enough to put it over the edge on jitter sensitivity. What happens if
> you provide cooling (fan) on the chip?
>
> -Jeff
>
>> Jeff Brower wrote:
>>
>>>Andrew-
>>>
>>>
>>>
>>>>Has anyone else come across problems using spread spectrum clock
>>>>generator (SSCG) chips for EMI reduction ?
>>>>
>>>>We use a C6713 that gets its clock from a Cypress CY25811 SSCG that is
>>>>used for EMI reduction. The problem is that our code crashes after
>>>>2-40 hours with the SSCG in place. If we disable the spread spectrum
>>>>feature of the same chip everything seems to run fine.
>>>>
>>>>Are there any known issues when using SSCGs with DSPs ?
>>>>
>>>>
>>>
>>> TI DSPs are sensitive to clock jitter, always have been. What is
>>> your maximum
>>> frequency % deviation? What is the modulation waveform and period?
>>>
>>> -Jeff
>>
Reply by ●August 24, 20062006-08-24
Andrew-
> Did try smaller spread spectrum deviation - to no affect.
> The chip we are using doesn't allow us to reduce the period.
>
> Yes, it did used to work with the 6713. The other variable that I didn't
> mention is that we use a PCI2040 to communicate with the 6713 via its
> HPI interface. The PCI2040 provides a slave PCI interface. It turns out
> that the failure is dependant on the PC we put the card in as well. It
> is as if certain newer PCs cause HPI transaction sequences that somehow
> interact with the effects the SSCG has on the 6713. All complicated and
> difficult to pin down.
Ok... I would check the PCI2040's timing when checking HRDY, which is the
most asynchronous, code-dependent signal in the mix vs. the 33 MHz PCI
clock. HCS has to be enabled first, and if the PCI2040's timing on this
is really tight, then a clock fluctuation might be killer.
> For the moment we have disabled the SSCG and will be retesting EMI.
> Maybe there are some other options for reducing EMI.
Ya, a big piece of tin foil over the 6713, haha.
-Jeff
> Jeff Brower wrote:
>
>> Andrew-
>>
>>> Deviation is +/- 1.2 %.
>>> Modulation waveform looks like a rounded off triangle wave.
>>> /\/\/\/\/\/\ type thing.
>>> Modulation period is 47 kHz, which corresponds to a period of ~20 usec.
>> This doesn't seem that aggressive. I'm sure you tried less deviation
>> and longer period -- did that achieve reliability?
>>
>>> Just heard back from TI support that they don't have a spec. for
>>> acceptable clock jitter. Problem is that we need SSCG to reduce EMI
>>> for FCC.
>>>
>>> Weird thing is that we have been using TI DSPs for some 10+ years and
>>> haven't run in to this before.
>>> Did it used to work with 6713? Any changes -- faster clock rate,
>> differnt PLL multiplier, new silicon revision? Maybe it's just
>> borderline, and you added more code, more DMA channels, etc (more
>> overall 'demand' on the chip) so the chip runs slightly hotter, just
>> enough to put it over the edge on jitter sensitivity. What happens if
>> you provide cooling (fan) on the chip?
>>
>> -Jeff
>>
>>> Jeff Brower wrote:
>>>
>>>>Andrew-
>>>>
>>>>
>>>>
>>>>>Has anyone else come across problems using spread spectrum clock
>>>>>generator (SSCG) chips for EMI reduction ?
>>>>>
>>>>>We use a C6713 that gets its clock from a Cypress CY25811 SSCG that is
>>>>>used for EMI reduction. The problem is that our code crashes after
>>>>>2-40 hours with the SSCG in place. If we disable the spread spectrum
>>>>>feature of the same chip everything seems to run fine.
>>>>>
>>>>>Are there any known issues when using SSCGs with DSPs ?
>>>>>
>>>>>
>>>>
>>>> TI DSPs are sensitive to clock jitter, always have been. What is
>>>> your maximum
>>>> frequency % deviation? What is the modulation waveform and period?
>>>>
>>>> -Jeff
>>>
> Did try smaller spread spectrum deviation - to no affect.
> The chip we are using doesn't allow us to reduce the period.
>
> Yes, it did used to work with the 6713. The other variable that I didn't
> mention is that we use a PCI2040 to communicate with the 6713 via its
> HPI interface. The PCI2040 provides a slave PCI interface. It turns out
> that the failure is dependant on the PC we put the card in as well. It
> is as if certain newer PCs cause HPI transaction sequences that somehow
> interact with the effects the SSCG has on the 6713. All complicated and
> difficult to pin down.
Ok... I would check the PCI2040's timing when checking HRDY, which is the
most asynchronous, code-dependent signal in the mix vs. the 33 MHz PCI
clock. HCS has to be enabled first, and if the PCI2040's timing on this
is really tight, then a clock fluctuation might be killer.
> For the moment we have disabled the SSCG and will be retesting EMI.
> Maybe there are some other options for reducing EMI.
Ya, a big piece of tin foil over the 6713, haha.
-Jeff
> Jeff Brower wrote:
>
>> Andrew-
>>
>>> Deviation is +/- 1.2 %.
>>> Modulation waveform looks like a rounded off triangle wave.
>>> /\/\/\/\/\/\ type thing.
>>> Modulation period is 47 kHz, which corresponds to a period of ~20 usec.
>> This doesn't seem that aggressive. I'm sure you tried less deviation
>> and longer period -- did that achieve reliability?
>>
>>> Just heard back from TI support that they don't have a spec. for
>>> acceptable clock jitter. Problem is that we need SSCG to reduce EMI
>>> for FCC.
>>>
>>> Weird thing is that we have been using TI DSPs for some 10+ years and
>>> haven't run in to this before.
>>> Did it used to work with 6713? Any changes -- faster clock rate,
>> differnt PLL multiplier, new silicon revision? Maybe it's just
>> borderline, and you added more code, more DMA channels, etc (more
>> overall 'demand' on the chip) so the chip runs slightly hotter, just
>> enough to put it over the edge on jitter sensitivity. What happens if
>> you provide cooling (fan) on the chip?
>>
>> -Jeff
>>
>>> Jeff Brower wrote:
>>>
>>>>Andrew-
>>>>
>>>>
>>>>
>>>>>Has anyone else come across problems using spread spectrum clock
>>>>>generator (SSCG) chips for EMI reduction ?
>>>>>
>>>>>We use a C6713 that gets its clock from a Cypress CY25811 SSCG that is
>>>>>used for EMI reduction. The problem is that our code crashes after
>>>>>2-40 hours with the SSCG in place. If we disable the spread spectrum
>>>>>feature of the same chip everything seems to run fine.
>>>>>
>>>>>Are there any known issues when using SSCGs with DSPs ?
>>>>>
>>>>>
>>>>
>>>> TI DSPs are sensitive to clock jitter, always have been. What is
>>>> your maximum
>>>> frequency % deviation? What is the modulation waveform and period?
>>>>
>>>> -Jeff
>>>
Reply by ●August 24, 20062006-08-24
Andrew-
> Deviation is +/- 1.2 %.
> Modulation waveform looks like a rounded off triangle wave.
> /\/\/\/\/\/\ type thing.
> Modulation period is 47 kHz, which corresponds to a period of ~20 usec.
This doesn't seem that aggressive. I'm sure you tried less deviation and longer
period -- did that achieve reliability?
> Just heard back from TI support that they don't have a spec. for acceptable clock
> jitter. Problem is that we need SSCG to reduce EMI for FCC.
>
> Weird thing is that we have been using TI DSPs for some 10+ years and haven't run
> in to this before.
Did it used to work with 6713? Any changes -- faster clock rate, differnt PLL
multiplier, new silicon revision? Maybe it's just borderline, and you added more
code, more DMA channels, etc (more overall 'demand' on the chip) so the chip runs
slightly hotter, just enough to put it over the edge on jitter sensitivity. What
happens if you provide cooling (fan) on the chip?
-Jeff
> Jeff Brower wrote:
>
>> Andrew-
>> > Has anyone else come across problems using spread spectrum clock
>> > generator (SSCG) chips for EMI reduction ?
>> >
>> > We use a C6713 that gets its clock from a Cypress CY25811 SSCG that is
>> > used for EMI reduction. The problem is that our code crashes after
>> > 2-40 hours with the SSCG in place. If we disable the spread spectrum
>> > feature of the same chip everything seems to run fine.
>> >
>> > Are there any known issues when using SSCGs with DSPs ?
>> >
>>
>> TI DSPs are sensitive to clock jitter, always have been. What is your maximum
>> frequency % deviation? What is the modulation waveform and period?
>>
>> -Jeff
>>
> Deviation is +/- 1.2 %.
> Modulation waveform looks like a rounded off triangle wave.
> /\/\/\/\/\/\ type thing.
> Modulation period is 47 kHz, which corresponds to a period of ~20 usec.
This doesn't seem that aggressive. I'm sure you tried less deviation and longer
period -- did that achieve reliability?
> Just heard back from TI support that they don't have a spec. for acceptable clock
> jitter. Problem is that we need SSCG to reduce EMI for FCC.
>
> Weird thing is that we have been using TI DSPs for some 10+ years and haven't run
> in to this before.
Did it used to work with 6713? Any changes -- faster clock rate, differnt PLL
multiplier, new silicon revision? Maybe it's just borderline, and you added more
code, more DMA channels, etc (more overall 'demand' on the chip) so the chip runs
slightly hotter, just enough to put it over the edge on jitter sensitivity. What
happens if you provide cooling (fan) on the chip?
-Jeff
> Jeff Brower wrote:
>
>> Andrew-
>> > Has anyone else come across problems using spread spectrum clock
>> > generator (SSCG) chips for EMI reduction ?
>> >
>> > We use a C6713 that gets its clock from a Cypress CY25811 SSCG that is
>> > used for EMI reduction. The problem is that our code crashes after
>> > 2-40 hours with the SSCG in place. If we disable the spread spectrum
>> > feature of the same chip everything seems to run fine.
>> >
>> > Are there any known issues when using SSCGs with DSPs ?
>> >
>>
>> TI DSPs are sensitive to clock jitter, always have been. What is your maximum
>> frequency % deviation? What is the modulation waveform and period?
>>
>> -Jeff
>>
