i run into a new problem,the video capture EDMA can't be trigered.i
configure video port0,port A to capture a standard 8-bit BT656 video data from
saa7113 encoder,continuous capture mode and to sent an interrupt request to CPU
when a complete line is captured.
but the edma interrupt can't be trigered,the edma interrupt service
routine can't be executed consequently.when i set the corresponding bit(bit
8 or edma interrupt) of interrupt flag register,the edma interrupt service
routine can be executed.so i doubt whether the video data has been captured into
the VP fifo.
below is my initialization code:
void dm642_video_init(uint32 addr)
{
uint32 i;
dm642_video_port0A_init();
dm642_video_port0A_edma_init(addr);
DM642_EDMA_ECRL = 0xffffffff;
DM642_EDMA_ECRH = 0xffffffff;
DM642_EDMA_CIPRL = 0xffffffff;
DM642_EDMA_CIPRH = 0xffffffff;
DM642_EDMA_CIERL = 0x0000001f;
DM642_EDMA_EERL = DM642_EDMA_EERL | (1 << DM642_EDMA_VP0A_Y_EVT) | (1 <<
DM642_EDMA_VP0A_U_EVT) | (1 << DM642_EDMA_VP0A_V_EVT);
DM642_VP0_CTL |= 0x00004000; //Dual channel video capture
DM642_VP0A_CTL |= 0x00008000;//0x00038590
DM642_VP0A_CTL &= 0xbfffffff;
}
void dm642_video_port0A_edma_init(uint32 addr)
{
EDMA_PaRAM edma_param;
uint32 evid;
edma_param.opt_pri = EDMA_PaRAM_OPT_PRI_HIGH;
edma_param.opt_esize = EDMA_PaRAM_OPT_ESIZE_32BIT;
edma_param.opt_2ds = EDMA_PaRAM_OPT_2DS_NO;
edma_param.opt_sum = EDMA_PaRAM_OPT_SUM_FIXED;
edma_param.opt_2dd = EDMA_PaRAM_OPT_2DD_YES;
edma_param.opt_dum = EDMA_PaRAM_OPT_DUM_INC;
edma_param.opt_tcint = EDMA_PaRAM_OPT_TCINT_NO;
edma_param.opt_tcc = 0;
edma_param.opt_tccm = 0;
edma_param.opt_atcint = EDMA_PaRAM_OPT_ATCINT_NO;
edma_param.opt_atcc = 0;
edma_param.opt_pdts = 0; //EDMA_PaRAM_OPT_PDTS_ENABLE;
edma_param.opt_pdtd = 0; //EDMA_PaRAM_OPT_PDTD_ENABLE;
edma_param.opt_link = EDMA_PaRAM_OPT_LINK_YES;
edma_param.opt_fs = EDMA_PaRAM_OPT_FS_NO;
edma_param.src = 0x74000000;
edma_param.cnt_frmcnt = 288 - 1;
edma_param.idx_eleidx = 0;
edma_param.cnt_elecnt = 352 / 4;
edma_param.idx_frmidx = 352;
edma_param.rld_elerld = 352 / 4;
//EDMA EVENT PARAMETER INITIAL
//VIDEO PORT Y ELEMENT
edma_param.opt_tcint = EDMA_PaRAM_OPT_TCINT_YES;
evid = 0; //DM642_EDMA_VP0A_Y_EVT;
edma_param.opt_tcc = evid % 16;
edma_param.opt_tccm = evid / 16;
edma_param.dst = addr;
edma_param.rld_link = DM642_EDMA_VP0A_Y_F1_DST2_EVT * 24;
dm642_edma_channel_init(DM642_EDMA_VP0A_Y_EVT, &edma_param);
dm642_edma_channel_init(DM642_EDMA_VP0A_Y_F1_DST1_EVT, &edma_param);
evid++;
edma_param.opt_tcc = evid % 16;
edma_param.opt_tccm = evid / 16;
edma_param.dst = addr + VIDEO_FRAME_DATA_COUNT;
edma_param.rld_link = DM642_EDMA_VP0A_Y_F1_DST3_EVT * 24;
dm642_edma_channel_init(DM642_EDMA_VP0A_Y_F1_DST2_EVT, &edma_param);
evid++;
edma_param.opt_tcc = evid % 16;
edma_param.opt_tccm = evid / 16;
edma_param.dst = addr + VIDEO_FRAME_DATA_COUNT + VIDEO_FRAME_DATA_COUNT;
edma_param.rld_link = DM642_EDMA_VP0A_Y_F1_DST1_EVT * 24;
dm642_edma_channel_init(DM642_EDMA_VP0A_Y_F1_DST3_EVT, &edma_param);
edma_param.opt_tcint = EDMA_PaRAM_OPT_TCINT_NO;
edma_param.opt_tcc = 0;
edma_param.opt_tccm = 0;
//VIDEO PORT U ELEMENT
edma_param.src = 0x74000008;
edma_param.cnt_elecnt = 176 / 4;
edma_param.dst = addr + 352*288;
edma_param.idx_frmidx = 176;
edma_param.rld_elerld = 176 / 4;
edma_param.rld_link = DM642_EDMA_VP0A_U_F1_DST2_EVT * 24;
dm642_edma_channel_init(DM642_EDMA_VP0A_U_EVT, &edma_param);
dm642_edma_channel_init(DM642_EDMA_VP0A_U_F1_DST1_EVT, &edma_param);
edma_param.dst = addr + VIDEO_FRAME_DATA_COUNT + 352*288;
edma_param.rld_link = DM642_EDMA_VP0A_U_F1_DST3_EVT * 24;
dm642_edma_channel_init(DM642_EDMA_VP0A_U_F1_DST2_EVT, &edma_param);
edma_param.dst = addr + VIDEO_FRAME_DATA_COUNT + VIDEO_FRAME_DATA_COUNT
+ 352*288;
edma_param.rld_link = DM642_EDMA_VP0A_U_F1_DST1_EVT * 24;
dm642_edma_channel_init(DM642_EDMA_VP0A_U_F1_DST3_EVT, &edma_param);
//VIDEO PORT V ELEMENT
edma_param.src = 0x74000010;
edma_param.dst = addr + 352*288 + 176*288;
edma_param.rld_link = DM642_EDMA_VP0A_V_F1_DST2_EVT * 24;
dm642_edma_channel_init(DM642_EDMA_VP0A_V_EVT, &edma_param);
dm642_edma_channel_init(DM642_EDMA_VP0A_V_F1_DST1_EVT, &edma_param);
edma_param.dst = addr + VIDEO_FRAME_DATA_COUNT + 352*288 + 176*288;
edma_param.rld_link = DM642_EDMA_VP0A_V_F1_DST3_EVT * 24;
dm642_edma_channel_init(DM642_EDMA_VP0A_V_F1_DST2_EVT, &edma_param);
edma_param.dst = addr + VIDEO_FRAME_DATA_COUNT + VIDEO_FRAME_DATA_COUNT
+ 352*288 +
176*288;
edma_param.rld_link = DM642_EDMA_VP0A_V_F1_DST1_EVT * 24;
dm642_edma_channel_init(DM642_EDMA_VP0A_V_F1_DST3_EVT, &edma_param);
}
void dm642_video_port0A_init(void)
{
DM642_VP0_PCR = 0x00000005;
DM642_VP0_CTL = 0x00000001;//Dual channel
DM642_VP0A_F1STRT = 8 | (1 << 16);
DM642_VP0A_F1STOP = (352 + 8 - 1) | (288 << 16);
DM642_VP0A_F2STRT = 8 | (1 << 16);
DM642_VP0A_F2STOP = (352 + 8 - 1) | (288 << 16);
DM642_VP0A_THRLD = (352 >> 3) | ((352 >> 3) << 16);
DM642_VP0A_EVTCT = 0x01200120;
DM642_VP0A_CTL = 0x40030590;
DM642_VP0_PFUNC = 0x00300000;
DM642_VP0_PDIR = 0x00300000;
DM642_VP0_PDOUT = 0x00300000;
DM642_VP0_IS = 0xffffffff;
DM642_VP0_IE = 0x000000cf;
}
