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McBSP with DMA

Started by pablo fraile May 7, 2002
Hi all!
I'm trying to configure a McBSP transfer between two C6202 using DMA events
both to transmit and receive data. The process is ok, except that data
received is shifted by two bytes (first two values are nonsense). I'm I
loosing something? If it helps, I include the config for both ports

RX TX
McBSP: McBSP:
SPCR = 0x00000000 SPCR = 0x00000000
RCR = 0x00020000 RCR = 0x00020000
XCR = 0x00020000 XCR = 0x00020000
SCGR = 0x20000007 SCGR = 0x20000007
MCR = 0x00000000 MCR = 0x00000000
RCER = 0x00000000 RCER = 0x00000000
XCER = 0x00000000 XCER = 0x00000000
PCR = 0x00000A00 PCR = 0x00000A00

DMA: DMA:
PRI = 0xC3681240 PRI = 0x33701210
SEC = 0x00080080 SEC = 0x00080080

Thanks in advance ''~``
( o o )
+-----------------.oooO--(_)--Oooo.-----------------+
| |
| PABLO FRAILE |
| .oooO |
| ( ) Oooo. |
+--------------------\ (----( )-------------------+
\_) ) /
(_/



Hi pablo,
While working with the TMS320C6711 there was an issue we had with
the EDMA and MCBSP's. It is rather subtle. Since I am not familiar with
the C6202, I do not know if the information below is relevant. Nonetheless
here it is Basically, we found issues in handling (E)DMA transfers to off chip memory
with 4-way caching enabled (i.e. all of the on chip memory was configured as
cache). The issue was likely that a DMA to an off-chip memory location
would produce a cache mis-match which could cause a replacement of the DMA'd
data when the cache controller wrote back to off-chip memory. Turning off
cache solves the problem. An alternate route we chose however, was to
configure on-chip memory as 3/4 cache and 1/4 SRAM and put our DMA buffers
in SRAM.

-Brad

-----Original Message-----
From: pablo fraile [mailto:]
Sent: Tuesday, May 07, 2002 12:26 AM
To: C6x@Yahoogroups. Com
Subject: [c6x] McBSP with DMA Hi all!
I'm trying to configure a McBSP transfer between two C6202 using DMA
events both to transmit and receive data. The process is ok, except that
data received is shifted by two bytes (first two values are nonsense). I'm I
loosing something? If it helps, I include the config for both ports

RX TX
McBSP: McBSP:
SPCR = 0x00000000 SPCR = 0x00000000
RCR = 0x00020000 RCR = 0x00020000
XCR = 0x00020000 XCR = 0x00020000
SCGR = 0x20000007 SCGR = 0x20000007
MCR = 0x00000000 MCR = 0x00000000
RCER = 0x00000000 RCER = 0x00000000
XCER = 0x00000000 XCER = 0x00000000
PCR = 0x00000A00 PCR = 0x00000A00

DMA: DMA:
PRI = 0xC3681240 PRI = 0x33701210
SEC = 0x00080080 SEC = 0x00080080

Thanks in advance ''~``
( o o )
+-----------------.oooO--(_)--Oooo.-----------------+
| |
| PABLO FRAILE |
| .oooO |
| ( ) Oooo. |
+--------------------\ (----( )-------------------+
\_) ) /
(_/ _____________________________________
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