Hye
i am sending data to EMIFA on C6416. by just small piece of code
while(1)
{
*output=0x0002136;
*output=0x0000000;
}
it continiously send 0002136 and 0000000 to EMIFA. i am using CE2 address to
send these values on EMIFA.
the problem is that EMIF clk out is 120 Mhz and data is coming out on 60 Mhz .
each values remain on port for 8 clk cycles. how can i reduce this?. please tell
me which register i should confire. i have configured the CE space control
register and tried to change the setup and hold values ...please help me
regarding this..
and thanks for all the help i got from this group and from jeff regarding EMIF
clk .i get to know alot about DSP processor . i found this group really
helpful.
Regards Muneeb
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EMIF data
Started by ●April 30, 2007
Reply by ●April 30, 20072007-04-30
Muneeb-
> i am sending data to EMIFA on C6416. by just small piece of code while(1)
> {
> *output=0x0002136;
> *output=0x0000000;
>
> } it continiously send 0002136 and 0000000 to EMIFA. i am using CE2 address to
> send these values on EMIFA.the problem is that EMIF clk out is 120 Mhz and data is
> coming out on 60 Mhz . each values remain on port for 8 clk cycles. how can i
> reduce this?. please tell me which register i should confire. i have configured the
> CE space control register and tried to change the setup and hold values ...please
> help me regarding this..and thanks for all the help i got from this group and from
> jeff regarding EMIF clk .i get to know alot about DSP processor . i found this
> group really helpful.
Well, that's just some C code -- who knows what's really happening. You need to look
at the actual asm code generated by the compiler to see how many instructions are
occurring between those to outputs -- maybe there are 12 instructions.
But in any case, the fastest method is not to use "manual CPU code". The fastest
method will be to use EDMA, allowing automated onchip DMA circuitry to transfer a
word on every ECLK edge. You can set up a small C code array and configure EDMA to
test this.
-Jeff
> i am sending data to EMIFA on C6416. by just small piece of code while(1)
> {
> *output=0x0002136;
> *output=0x0000000;
>
> } it continiously send 0002136 and 0000000 to EMIFA. i am using CE2 address to
> send these values on EMIFA.the problem is that EMIF clk out is 120 Mhz and data is
> coming out on 60 Mhz . each values remain on port for 8 clk cycles. how can i
> reduce this?. please tell me which register i should confire. i have configured the
> CE space control register and tried to change the setup and hold values ...please
> help me regarding this..and thanks for all the help i got from this group and from
> jeff regarding EMIF clk .i get to know alot about DSP processor . i found this
> group really helpful.
Well, that's just some C code -- who knows what's really happening. You need to look
at the actual asm code generated by the compiler to see how many instructions are
occurring between those to outputs -- maybe there are 12 instructions.
But in any case, the fastest method is not to use "manual CPU code". The fastest
method will be to use EDMA, allowing automated onchip DMA circuitry to transfer a
word on every ECLK edge. You can set up a small C code array and configure EDMA to
test this.
-Jeff
