Dakys-
> I got the answer for the max bandwidth of the SDRAM,
can you please help in the second question?
I believe the DMA transfers would not take place exactly at the same instant,
but
instead would appear on a dig scope as interleaved. From a software
perspective,
they would appear to take place concurrently. Two concurrent transfers could
be
somewhat slower than if only one transfer was occurring, since they both may
compete
with each other and the CPU for access to internal memory busses.
One other comment -- I suggest you connect EMIFA to SDRAM and EMIFB to the FPGA.
There are a number of reasons for this that become apparent if you look through
the
data sheet, including boot config Rs attached to EMIFB lines.
-Jeff
> dakys sola a rit :
Hi all,
>
> I'm new in DSP. Could you please help me in finding the max SDRAM
bandwidth in a C6415 DSP?
> Something else, I want to connect my DSP to a FPGA through EMIFA and use
EMIFB for transfers between DSP and SDRAM. If I use DMA for both transfers,
could these transfers be done simultanously?
>
> Best Regards,
> Dakys
