Hello everybody, I'm working with DM642 DSP device and I would like to use
the DAT CSL module.
At present time I'm testing it through the following code:
bufLap_loc = (label_type *)MEM_valloc(HEAP_L2SRAM, lx*ly2*sizeof(short int),
0,0);
bufGauss_loc = (label_type *)MEM_valloc(HEAP_L2SRAM, lx*ly2*sizeof(short
int),0,0);
imgy_loc = (pixel_type *)MEM_valloc(HEAP_L2SRAM,
(lx+6)*ly2*sizeof(char),0,0);
CACHE_wbInvAllL2(CACHE_WAIT);
transferId = DAT_open (
DAT_CHAANY,
DAT_PRI_LOW,
DAT_OPEN_2D
);
transferId = DAT_copy2d(
DAT_2D1D,
img,
imgy_loc,
SIZE,
6,
(Uint16)(xdim*sizeof(char))
);
DAT_wait(transferId);
However if SIZE%2==0 the transfer is ok, but if SIZE%2==1 and I compare img
against imgy_loc after the DMA_wait, the cell 1,3,5 of imgy_loc and img are
equals, while 0,2,4 differ.
Is there some hint about the size of the base transfer unit for DM642? I know
that there is some hint about memory alignment in order to improve performance,
but it is not a constraint, or at least I didn't found such a
constraint.
Any help will be appreciated
