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Hi, I am new to this group. I am using TMS320C6416 DSP on a 3G-derivative base station design, and would like to get some inputs on how to efficiently organize the DSP cache memory. In the design, the host CPU sends downlink data to DSP, and the DSP does the baseband symbol processing. Then the data is sent to an ASIC chip for further chip-rate processing. For the uplink, the DSP gets the data from an ASIC, does some symbol rate processing and ask the host to DMA the data to host CPU. So in my mind the various data transfers to DSP are: 1. Host CPU ---> DSP #send dl data to DSP 2. Host CPU <--- DSP #recieve UL data from DSP. 3. DSP ---> ASIC #DSP sends DL data to ASIC for chip rate processing. 4. DSP <--- ASIC #DSP recieves UL data from ASIC for symbol rate processing. 5. DSP ---> DSP # data exchange between adjacent DSP. 6. regular L1P <--> L2 and L1D <--> L2 transfer. The DSP has no controls on when the first two transfers happen. It is likely that the transfers between the host and DSP will be slow relative to the DSP clock speed. If the L2 is configured as all SRAM, I am afraid that allowing the host direct accesses to L2 might create serous contention on L2 accesses for other parts of the DSP. Does anyone have some ideas how serious that might be? Alternately, I can put a DPRAM between the host CPU and DSP (Host still has HPI/PCI to DSP) so that host can freely send/receive data to DPRAM, and DSP can also access the DPRAM at a higher EMIFx clock speed at a time controled by DSP. Is it normally to put DPRAM on a cache memory design. Does anyone know how the L2 memory banks are divided into 4 64-bit banks? Are sequential double words in different banks? Thanks in advance. Wilson |
C6416 cache
Started by ●August 2, 2002
