When is a fractional-N PLL needed?

Started by gretzteam August 4, 2010
Hi,
I'm trying to understand when a fractional-N PLL is required. I'm doing
this in an FPGA so it's an ADPLL, but I think my questions are basic enough
that it applies to any PLL. 

When using a basic PLL topology:

ref -> PFD -> LPF -> NCO -> output
         |                    |
         |<-------div-N<------|

I can only create output clocks that are at an integer multiple of the
reference input. For example, if ref=10kHz, I can create 20, 30, 40...

Say I would like to be able to generate 52kHz. I see two ways:

1) Keep the exact same topology, but add a div-M at the output of the
system. This way, I could set div-N=52, making the output 520kHz, and
div-M=10, essentially getting my back to 52kHz. However, even for trivial
output clock value, the N divider can get quite high which makes the whole
thing harder to design.

2) Have the div-N value change between 5 and 6 in a way that it's 5.2 on
average (probably a sigma-delta modulator would control this). This doesn't
seem to have the disadvantage of option 1, but opens-up a whole new level
of difficulty with the sigma-delta modulator etc...

Am I understanding the trade-offs correctly, or I'm way out in left field?

Thanks!
gretzteam <gretzteam@n_o_s_p_a_m.yahoo.com> wrote:

>I'm trying to understand when a fractional-N PLL is required.
For some sets of design constraints, the fractional-N approach leads to lower phase noise than non-fractional-N approaches. This is (probably) the main reason it is used. S.
On 08/04/2010 10:23 AM, gretzteam wrote:
> Hi, > I'm trying to understand when a fractional-N PLL is required. I'm doing > this in an FPGA so it's an ADPLL, but I think my questions are basic enough > that it applies to any PLL. > > When using a basic PLL topology: > > ref -> PFD -> LPF -> NCO -> output > | | > |<-------div-N<------| > > I can only create output clocks that are at an integer multiple of the > reference input. For example, if ref=10kHz, I can create 20, 30, 40... > > Say I would like to be able to generate 52kHz. I see two ways: > > 1) Keep the exact same topology, but add a div-M at the output of the > system. This way, I could set div-N=52, making the output 520kHz, and > div-M=10, essentially getting my back to 52kHz. However, even for trivial > output clock value, the N divider can get quite high which makes the whole > thing harder to design. > > 2) Have the div-N value change between 5 and 6 in a way that it's 5.2 on > average (probably a sigma-delta modulator would control this). This doesn't > seem to have the disadvantage of option 1, but opens-up a whole new level > of difficulty with the sigma-delta modulator etc... > > Am I understanding the trade-offs correctly, or I'm way out in left field?
3) lower the reference frequency to 2kHz (or raise it to 13kHz for your specific example). Touching on Steve's comment, for some synthesizers you can get lower phase noise with the fractional-N division (and proper filtering of the phase error) than you can by lowering the reference frequency (which is one other option). -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html
On Wed, 04 Aug 2010 12:23:24 -0500, gretzteam wrote:

> Hi, > I'm trying to understand when a fractional-N PLL is required. I'm doing > this in an FPGA so it's an ADPLL, but I think my questions are basic > enough that it applies to any PLL. > > When using a basic PLL topology: > > ref -> PFD -> LPF -> NCO -> output > | | > |<-------div-N<------| > > I can only create output clocks that are at an integer multiple of the > reference input. For example, if ref=10kHz, I can create 20, 30, 40... > > Say I would like to be able to generate 52kHz. I see two ways: > > 1) Keep the exact same topology, but add a div-M at the output of the > system. This way, I could set div-N=52, making the output 520kHz, and > div-M=10, essentially getting my back to 52kHz. However, even for > trivial output clock value, the N divider can get quite high which makes > the whole thing harder to design.
Dividers are easy to design and cheap to implement. The real problem is that the PFD frequency is lower, which leads to (usually) undesirable tradeoffs with the loop filter, phase noise, reference spurs, etc.
> 2) Have the div-N value change between 5 and 6 in a way that it's 5.2 on > average (probably a sigma-delta modulator would control this). This > doesn't seem to have the disadvantage of option 1, but opens-up a whole > new level of difficulty with the sigma-delta modulator etc...
Again, these aren't too hard to design, and usually worth the effort.
> Am I understanding the trade-offs correctly, or I'm way out in left > field?
You seem to be on the right track. I present the following alternative (and less practical) methods for interest. Approach #2b: Use another NCO for the feedback divider. This produces an average division of 5.2, but unlike the sigma-delta modulator, the phase modulation produced is deterministic. The output spectrum will have strong spurs (as opposed to the continuous noisy spectrum produced by the sigma delta one). I have seen (analog) PLLs attempt to estimate this effect and inject a saw tooth shaped current into the PFD output to cancel it. About 20dB spur reduction can be achieved - this is limited by the accuracy and frequency response of the DACs employed. I don't know whether this is used in contemporary parts, but it is an interesting technique nonetheless. I believe chip designers stopped doing this when they figured out how to design sigma delta modulators. Approach #3: Use a mixer to translate the output frequency by some offset. This is easy to do if the signals are sinusoidal (in which case the mixer is just a complex multiplier) but a little difficult if they are square waves (which I guess would be commonly used inside a DPLL). The mixer is placed between the output and the feedback divider. Example: Divide the 10kHz down to 2kHz, and generate a sinewave at this frequency. Use it to mix the 52kHz PLL output down to 50kHz, then put that into the feedback divider, which produces the 10kHz that goes into the PFD. I've never seen that approach used in a DPLL (particularly one in an FPGA). Approach #4: Use a VCO at a frequency much higher than you need, then divide it down to the frequency you want. (Again, this isn't applicable for a DPLL inside an FPGA.) There are plenty of cheap analog frequency synthesiser chips available that have ring-oscillator VCOs that operate in the range 1-2GHz. They usually have the dividers you need on-chip as well. You'll need to use one that allows the use of an external loop filter, as the on- chip loop filters usually result in bws of some MHz and your reference is only 10kHz. Cheers, Allan
On Wed, 04 Aug 2010 23:19:21 +0000, Allan Herriman wrote:

> On Wed, 04 Aug 2010 12:23:24 -0500, gretzteam wrote: > >> Hi, >> I'm trying to understand when a fractional-N PLL is required. I'm doing >> this in an FPGA so it's an ADPLL, but I think my questions are basic >> enough that it applies to any PLL. >> >> When using a basic PLL topology: >> >> ref -> PFD -> LPF -> NCO -> output >> | | >> |<-------div-N<------| >> >> I can only create output clocks that are at an integer multiple of the >> reference input. For example, if ref=10kHz, I can create 20, 30, 40... >> >> Say I would like to be able to generate 52kHz. I see two ways: >> >> 1) Keep the exact same topology, but add a div-M at the output of the >> system. This way, I could set div-N=52, making the output 520kHz, and >> div-M=10, essentially getting my back to 52kHz. However, even for >> trivial output clock value, the N divider can get quite high which >> makes the whole thing harder to design. > > Dividers are easy to design and cheap to implement. The real problem is > that the PFD frequency is lower, which leads to (usually) undesirable > tradeoffs with the loop filter, phase noise, reference spurs, etc.
Oops, I see I missed something there. (I thought you were talking about a divider on the reference input rather than the NCO output.) I hope you found the rest of the post entertaining though.
> > Cheers, > Allan
On Aug 4, 7:25=A0pm, Allan Herriman <allanherri...@hotmail.com> wrote:
> On Wed, 04 Aug 2010 23:19:21 +0000, Allan Herriman wrote: > > On Wed, 04 Aug 2010 12:23:24 -0500, gretzteam wrote: > > >> Hi, > >> I'm trying to understand when a fractional-N PLL is required. I'm doin=
g
> >> this in an FPGA so it's an ADPLL, but I think my questions are basic > >> enough that it applies to any PLL. > > >> When using a basic PLL topology: > > >> ref -> PFD -> LPF -> NCO -> output > >> =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| > >> =A0 =A0 =A0 =A0 =A0|<-------div-N<------| > > >> I can only create output clocks that are at an integer multiple of the > >> reference input. For example, if ref=3D10kHz, I can create 20, 30, 40.=
..
> > >> Say I would like to be able to generate 52kHz. I see two ways: > > >> 1) Keep the exact same topology, but add a div-M at the output of the > >> system. This way, I could set div-N=3D52, making the output 520kHz, an=
d
> >> div-M=3D10, essentially getting my back to 52kHz. However, even for > >> trivial output clock value, the N divider can get quite high which > >> makes the whole thing harder to design. > > > Dividers are easy to design and cheap to implement. =A0The real problem=
is
> > that the PFD frequency is lower, which leads to (usually) undesirable > > tradeoffs with the loop filter, phase noise, reference spurs, etc. > > Oops, I see I missed something there. =A0(I thought you were talking abou=
t a
> divider on the reference input rather than the NCO output.) =A0I hope you > found the rest of the post entertaining though. > > > > > Cheers, > > Allan > >
if you need only to generate a fixed frequency there may not be any particular advantage to frac N. If, on the other hand, you need to create a tunable LO that has to tune to a set of channels and the channel spacing is low and you want the reference high for phase noise, that is where a frac N can help. For example if you need to have 1 kHz channel spacing with a int N you need the ref freq to be 1 kHz and this may be too low for good phase nosie. If you use a frac N, the ref can be 100 kHz and you can still get 1 kHz channel spacing Mark
> >3) lower the reference frequency to 2kHz (or raise it to 13kHz for your >specific example). > >Touching on Steve's comment, for some synthesizers you can get lower >phase noise with the fractional-N division (and proper filtering of the >phase error) than you can by lowering the reference frequency (which is >one other option). > >--
After reading all the posts, I can see that the extra div-M could be also placed at the reference input. This would avoid the need for a very fast NCO, but would have more phase noise. Intuitively, dividing the reference is effectively throwing away information. I guess the sigma-delta controlled div-N is the way to go. Now I'm not too sure about: a)Rate of the sigma-delta modulator. You probably want to update the divider value only every time one full 'division' was done, which would mean it's running at the reference input rate? b)Is it as simple as feeding the wanted 'fractional' value (0.2 in this example) into say a 1st order sigma-delta modulator? Then use the 1-bit output to choose between the two wanted integer (5 and 6 in this example)? Thanks a lot for the comments! Dave
On Aug 4, 1:23=A0pm, "gretzteam" <gretzteam@n_o_s_p_a_m.yahoo.com>
wrote:
> Hi, > I'm trying to understand when a fractional-N PLL is required. I'm doing > this in an FPGA so it's an ADPLL, but I think my questions are basic enou=
gh
> that it applies to any PLL. > > When using a basic PLL topology: > > ref -> PFD -> LPF -> NCO -> output > =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| > =A0 =A0 =A0 =A0 =A0|<-------div-N<------| > > I can only create output clocks that are at an integer multiple of the > reference input. For example, if ref=3D10kHz, I can create 20, 30, 40... > > Say I would like to be able to generate 52kHz.
why not just have two NCOs, both based on the signal coming out of the LPF, where the NCO connected in feedback has a div-1 (no frequency divider) and the other NCO is identical but works on a scaled (by a factor of 5.2) version of the output of the NCO? seems to me that it would work. r b-j
>On Aug 4, 1:23=A0pm, "gretzteam" <gretzteam@n_o_s_p_a_m.yahoo.com> >wrote: >> Hi, >> I'm trying to understand when a fractional-N PLL is required. I'm doing >> this in an FPGA so it's an ADPLL, but I think my questions are basic
enou=
>gh >> that it applies to any PLL. >> >> When using a basic PLL topology: >> >> ref -> PFD -> LPF -> NCO -> output >> =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| >> =A0 =A0 =A0 =A0 =A0|<-------div-N<------| >> >> I can only create output clocks that are at an integer multiple of the >> reference input. For example, if ref=3D10kHz, I can create 20, 30,
40...
>> >> Say I would like to be able to generate 52kHz. > >why not just have two NCOs, both based on the signal coming out of the >LPF, where the NCO connected in feedback has a div-1 (no frequency >divider) and the other NCO is identical but works on a scaled (by a >factor of 5.2) version of the output of the NCO? > >seems to me that it would work. > >r b-j
Hi r b-j Sorry I've only seen your reply now. I don't quite understand what you are saying about the two NCO. I would need a full blown divider to calculate the 2nd NCO increment value (the one outside the loop). Is this what you were saying? Dave
On 08/04/2010 07:52 PM, gretzteam wrote:
>> >> 3) lower the reference frequency to 2kHz (or raise it to 13kHz for your >> specific example). >> >> Touching on Steve's comment, for some synthesizers you can get lower >> phase noise with the fractional-N division (and proper filtering of the >> phase error) than you can by lowering the reference frequency (which is >> one other option). >> >> -- > > After reading all the posts, I can see that the extra div-M could be also > placed at the reference input. This would avoid the need for a very fast > NCO, but would have more phase noise. Intuitively, dividing the reference > is effectively throwing away information. > > I guess the sigma-delta controlled div-N is the way to go. > Now I'm not too sure about: > a)Rate of the sigma-delta modulator. You probably want to update the > divider value only every time one full 'division' was done, which would > mean it's running at the reference input rate? > > b)Is it as simple as feeding the wanted 'fractional' value (0.2 in this > example) into say a 1st order sigma-delta modulator? Then use the 1-bit > output to choose between the two wanted integer (5 and 6 in this example)?
Your last comment bubbled this thread up to the top, and I realized I never answered -- I was hoping that someone with more solid grounding in the subject would speak up. (a) -- yes. (b) Probably not, but maybe. You'd have to do the analysis for your system to see. I suspect that you'd want to put one or two additional poles of lowpass into your loop filter, and use a higher order modulator. But I've never actually done a fractional-N synthesizer; they came out after I'd moved on to things other than frequency synthesis. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html