Hi Guys Many thanks for your replies. Thanks to Rick and Glen for the links. So am I right to say that the following flow is correct: Antenna->AGC->ADC->Bandpass->Down Conversion->etc... The reason to put the AGC before ADC is to bring the incoming signal withing the dynamic range of the ADC. And it definitely looks like I need to study the front side of the receiver. Once again, thanks very much. Best Regards Chintan
A question on practical receiver
Started by ●September 23, 2010
Reply by ●September 23, 20102010-09-23
Reply by ●September 23, 20102010-09-23
Vladimir Vassilevsky <nospam@nowhere.com> wrote: (snip, I wrote)>> among others, it describes the use of new 12 bit, 3.6Gsps ADCs, >> and their use in SDR. Digitize the whole bandwidth and do all >> the filtering digitally.> This approach results in a combination of poor performance, > huge power consumption and high cost.They claim lower power. That is, the digital filters use less power than would be used by analog filters. Well, it seems one advantage that the paper is interested in is doing multiple channels at once. One receiver could demodulate all the AM broadcast frequencies. The power of the ADC is then divided among all the frequencies, where separate analog filters would be needed for each. You can implement a very large number of digital filters in a large FPGA. Now, why you want to do that is still a good question.>> It seems we might be close to the point where it is antenna, >> RF amplifier, ADC, and then a medium sized FPGA to do all the >> processing.> There are few areas where the SDR approach is viable; in most > cases good old analog is simpler, cheaper, smaller and better.But maybe not for so much longer. -- glen
Reply by ●September 23, 20102010-09-23
glen herrmannsfeldt wrote:> Vladimir Vassilevsky <nospam@nowhere.com> wrote: > (snip, I wrote) > > >>>among others, it describes the use of new 12 bit, 3.6Gsps ADCs, >>>and their use in SDR. Digitize the whole bandwidth and do all >>>the filtering digitally. > >>This approach results in a combination of poor performance, >>huge power consumption and high cost. > > They claim lower power. That is, the digital filters use less > power than would be used by analog filters.Even compared with passive filters ? :-) Digital processing burns at the order of 5e-9 J per MAC operation, however it allows for the efficient multichannel multirate tricks.> Well, it seems one advantage that the paper is interested in > is doing multiple channels at once. One receiver could demodulate > all the AM broadcast frequencies. The power of the ADC is then > divided among all the frequencies, where separate analog filters > would be needed for each.Then, the ADC should be N times better (at the very least) then required for single channel processing.> You can implement a very large number of digital filters > in a large FPGA. Now, why you want to do that is still > a good question.Nowadays, the technology for application is not a problem. Problem is an application for technology.>>>It seems we might be close to the point where it is antenna, >>>RF amplifier, ADC, and then a medium sized FPGA to do all the >>>processing. > >>There are few areas where the SDR approach is viable; in most >>cases good old analog is simpler, cheaper, smaller and better. > > But maybe not for so much longer.Maybe. Transistors were vastly inferior and expensive compared to the tubes initially. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
Reply by ●September 24, 20102010-09-24
On 09/23/2010 01:13 PM, cpshah99 wrote:> Hi Guys > > Many thanks for your replies. Thanks to Rick and Glen for the links. > > So am I right to say that the following flow is correct: > > Antenna->AGC->ADC->Bandpass->Down Conversion->etc... > > The reason to put the AGC before ADC is to bring the incoming signal > withing the dynamic range of the ADC.But doing so means that a strong interfering signal can blank the ADC completely. Moreover, doing it your way makes the system sensitive to the antenna bandwidth, with wider bandwidth antennas leaving the system more susceptible to blanking and distortion. If you know the frequency range that you want to receive in, it's much better to go Antenna -> Bandpass -> AGC -> ADC -> etc. Better yet, you should choose an ADC that just plain has the dynamic range you need, and leave the AGC out or make it part of the IF signal processing.> And it definitely looks like I need to study the front side of the > receiver.Receiver design is a complicated subject. There's certainly a lot there to study. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html
Reply by ●September 24, 20102010-09-24
On 09/23/2010 12:38 PM, Steve Pope wrote:> glen herrmannsfeldt<gah@ugcs.caltech.edu> wrote: > >> among others, it describes the use of new 12 bit, 3.6Gsps ADCs, >> and their use in SDR. Digitize the whole bandwidth and do all >> the filtering digitally. > >> It seems we might be close to the point where it is antenna, >> RF amplifier, ADC, and then a medium sized FPGA to do all the >> processing. > > SDR is valid for infrastructure but seldom the best way to design > the highest-volume radio products (mobile handsets, WLAN devises, > etc.) > > 12 bits may not actually be enough to remove a jammer that a superhet > design can routinely filter out.If I'm getting my math right, then the thermal noise on a 50 ohm resistor at room temperature with a 1.8GHz bandwidth should be a bit over 4mV. If you let that equal your ADC MSB, then the full ADC range will be +/- 6V. That's a whole lot of signal to see at the terminals of an antenna, and even if you encroach into that somewhat you're still going to have useful narrow band signal. So maybe the dynamic range of such a system wouldn't be all that bad, after all. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html
Reply by ●September 24, 20102010-09-24
Tim Wescott <tim@seemywebsite.com> wrote:>On 09/23/2010 12:38 PM, Steve Pope wrote: >> glen herrmannsfeldt<gah@ugcs.caltech.edu> wrote: >> >>> among others, it describes the use of new 12 bit, 3.6Gsps ADCs, >>> and their use in SDR. Digitize the whole bandwidth and do all >>> the filtering digitally. >> >>> It seems we might be close to the point where it is antenna, >>> RF amplifier, ADC, and then a medium sized FPGA to do all the >>> processing. >> >> SDR is valid for infrastructure but seldom the best way to design >> the highest-volume radio products (mobile handsets, WLAN devises, >> etc.) >> >> 12 bits may not actually be enough to remove a jammer that a superhet >> design can routinely filter out. > >If I'm getting my math right, then the thermal noise on a 50 ohm >resistor at room temperature with a 1.8GHz bandwidth should be a bit >over 4mV. If you let that equal your ADC MSB, then the full ADC range >will be +/- 6V. That's a whole lot of signal to see at the terminals of >an antenna, and even if you encroach into that somewhat you're still >going to have useful narrow band signal.>So maybe the dynamic range of such a system wouldn't be all that bad, >after all.I think the issue here is both your signal of interest, and your jammer, might be way smaller than 4 mV, because they are much more narrowband than 1.8 GHz. Possibly you might get some sort of processing gain in the digital domain, so that your 12 bits becomes 20 bits or whatever, and then you can filter out the interferers. But you better make sure your system actually behaves in that way. Generally in a receiver you want as much selectivity as possible as close to the front-end of the receiver as possible. This almost always means you want selectivity ahead of the ADC. Steve
Reply by ●September 24, 20102010-09-24
> > If I'm getting my math right, then the thermal noise on a 50 ohm > resistor at room temperature with a 1.8GHz bandwidth should be a bit > over 4mV. �I got -81 dBm or about 0.02mV RMS ???.. were you on the sun? :-) Mark
Reply by ●September 24, 20102010-09-24
On 09/24/2010 07:29 AM, Mark wrote:> >> >> If I'm getting my math right, then the thermal noise on a 50 ohm >> resistor at room temperature with a 1.8GHz bandwidth should be a bit >> over 4mV. > > I got -81 dBm or about 0.02mV RMS ???.. > > were you on the sun? :-)No, but you can check my math: resistor noise density at room temperature: 3.98fW / Hz. Resistor noise at 1.8GHz bandwidth: (3.98fW / Hz) * 1.8GHz = 7.2nW. This is your -81dBm, but we're doing something different with it from there (and I did make a boo-boo). 50 ohm resistor voltage at room temperature, 1.8GHz bandwidth: (Dayum -- I forgot to bring the resistance inside the square root sign. This is why we beat on the kids to show their work...) sqrt((50 ohm)(7.2nW)) = 600uV. So, you start limiting at 1.23V if you set your LSB equal to your resistor's noise floor (and frankly, the ADC noise figure is going to be way higher than 0dB). I'm not sure where your conversion from -81dBm at 50 ohms diverged from mine. But then, my "in the head" version was different from my "show your work, Tim" version. Three different answers! But I think this one is right. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html
Reply by ●September 24, 20102010-09-24
On 09/24/2010 08:56 AM, Tim Wescott wrote:> On 09/24/2010 07:29 AM, Mark wrote: >> >>> >>> If I'm getting my math right, then the thermal noise on a 50 ohm >>> resistor at room temperature with a 1.8GHz bandwidth should be a bit >>> over 4mV. >> >> I got -81 dBm or about 0.02mV RMS ???.. >> >> were you on the sun? :-) > > No, but you can check my math: > > resistor noise density at room temperature: 3.98fW / Hz. > > Resistor noise at 1.8GHz bandwidth: (3.98fW / Hz) * 1.8GHz = 7.2nW. This > is your -81dBm, but we're doing something different with it from there > (and I did make a boo-boo). > > 50 ohm resistor voltage at room temperature, 1.8GHz bandwidth: > > (Dayum -- I forgot to bring the resistance inside the square root sign. > This is why we beat on the kids to show their work...) > > sqrt((50 ohm)(7.2nW)) = 600uV. > > So, you start limiting at 1.23V if you set your LSB equal to your > resistor's noise floor (and frankly, the ADC noise figure is going to be > way higher than 0dB). > > I'm not sure where your conversion from -81dBm at 50 ohms diverged from > mine. But then, my "in the head" version was different from my "show > your work, Tim" version. Three different answers! But I think this one > is right.Mark was kind enough to let me know off the group, but I'd rather the error get corrected here -- I'm rusty with my calculations, and neglected to account for the fact that dBm is milliwatts, not watts. So his number is correct. Still not bad, but definitely getting down to where you'd like to do some band pass filtering before the ADC if you can (and you'd like to double check the noise performance of the ADC -- most of them really suck). -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html
Reply by ●September 24, 20102010-09-24
On 09/24/2010 01:19 AM, Steve Pope wrote:> Tim Wescott<tim@seemywebsite.com> wrote: > >> On 09/23/2010 12:38 PM, Steve Pope wrote: >>> glen herrmannsfeldt<gah@ugcs.caltech.edu> wrote: >>> >>>> among others, it describes the use of new 12 bit, 3.6Gsps ADCs, >>>> and their use in SDR. Digitize the whole bandwidth and do all >>>> the filtering digitally. >>> >>>> It seems we might be close to the point where it is antenna, >>>> RF amplifier, ADC, and then a medium sized FPGA to do all the >>>> processing. >>> >>> SDR is valid for infrastructure but seldom the best way to design >>> the highest-volume radio products (mobile handsets, WLAN devises, >>> etc.) >>> >>> 12 bits may not actually be enough to remove a jammer that a superhet >>> design can routinely filter out. >> >> If I'm getting my math right, then the thermal noise on a 50 ohm >> resistor at room temperature with a 1.8GHz bandwidth should be a bit >> over 4mV. If you let that equal your ADC MSB, then the full ADC range >> will be +/- 6V. That's a whole lot of signal to see at the terminals of >> an antenna, and even if you encroach into that somewhat you're still >> going to have useful narrow band signal. > >> So maybe the dynamic range of such a system wouldn't be all that bad, >> after all. > > I think the issue here is both your signal of interest, and your > jammer, might be way smaller than 4 mV, because they are much more > narrowband than 1.8 GHz. > > Possibly you might get some sort of processing gain in the digital > domain, so that your 12 bits becomes 20 bits or whatever, and > then you can filter out the interferers. But you better make > sure your system actually behaves in that way.As long as the ADC is reasonably linear then you would get all kinds of processing gain in the digital domain. Processing gain will, in fact, be pretty darn close to 1.8GHz / (signal bandwidth) (or maybe twice that -- as I mentioned elsewhere recently, I'm a bit rusty to do this off the top of my head).> Generally in a receiver you want as much selectivity as possible > as close to the front-end of the receiver as possible. This > almost always means you want selectivity ahead of the ADC.Agreed -- unless you needed a really, really, agile receiver. You want just enough selectivity ahead of the ADC (or first mixer), and no more. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.html
