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ADC bottleneck?

Started by Peter Mairhofer October 10, 2010
Hi,

Many papers argue that todays bottleneck is signal 
processing/communications is the ADC (because DSP is no problem because 
of Moore's law).

There are many approaches which promise to reduce the sampling rate such 
as compressed sensing or finite rate of innovation sampling (which do 
not (yet) work in practice).

On the other hand, there are cheap high resolution ADC available at in 
the Mhz range (the fastest ADC sample at 40 Ghz!). Communication systems 
based on OFDM for example sample the whole bandwidth (up to 20 Mhz) and 
do the rest in a DSP. ADCs in this range are so cheap (in serval 
aspects) that the new techniques mentioned above (with all their 
disadvantages) would not really benifit.

So what is the real bottleneck in *your* opinion? And which technology 
would really need faster ADC conversion in practise? UWB? ...?

Maybe I can motivate a small discussion :-)

Regards,
Peter


On Sun, 10 Oct 2010 22:39:54 +0200, Peter Mairhofer <63832452@gmx.net>
wrote:

>Hi, > >Many papers argue that todays bottleneck is signal >processing/communications is the ADC (because DSP is no problem because >of Moore's law). > >There are many approaches which promise to reduce the sampling rate such >as compressed sensing or finite rate of innovation sampling (which do >not (yet) work in practice). > >On the other hand, there are cheap high resolution ADC available at in >the Mhz range (the fastest ADC sample at 40 Ghz!). Communication systems >based on OFDM for example sample the whole bandwidth (up to 20 Mhz) and >do the rest in a DSP. ADCs in this range are so cheap (in serval >aspects) that the new techniques mentioned above (with all their >disadvantages) would not really benifit. > >So what is the real bottleneck in *your* opinion? And which technology >would really need faster ADC conversion in practise? UWB? ...?
High speed ADCs are 'a' bottleneck and there are two way to address them: subband sampling and dynamic calibration. In most high frequency systems the signal doesn't use all the range from dc to max frequency so a sampling rate which would fold the actual signal to something reasonable without any aliasing is a perfectly acceptable process. Another possibility which doesn't need "perfect" ADCs is to do dynamic calibration/correction which follows the ADC with a digital correction/calibration block which corrects most of the linear (and even some non-linear) distortion an ADC causes. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com

Peter Mairhofer wrote:

> Hi, > > Many papers argue that todays bottleneck is signal > processing/communications is the ADC (because DSP is no problem because > of Moore's law).
Name one paper.
> So what is the real bottleneck in *your* opinion? And which technology > would really need faster ADC conversion in practise? UWB? ...?
The bottleneck are stupid people asking questions with the global scope.
> Maybe I can motivate a small discussion :-)
There are only two problems: who is going to pay and why he is willing to pay. VLV