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Loop Bandwidth and PLL understanding

Started by aizza ahmed October 7, 2011
Hello Everybody,
         Thanks to all experts, i am learning a lot from this group.
after studying good amount of literature, i see that the terminology
Loop Bandwidth is more applicable to Analog PLL. Say in Costal PLL,
the more accurate terminologies are Cut-Off frequency of the LPFs and
the quiescient frequency of the NCO. kindly confirm ??

Also i see in matlab simulations on central file exchange, there are
two sets of simulations

1. with the Loop Bandwidth, alpha,zeta, c1 and c2 factors. what is
this PLL called and where and how it is used in digital modulation
schemes like bpsk,qpsk and others.
2. plain 3 LPF + NCO based PLL. what is this PLL called and how it is
used in qpsk,bpsk and others and how this PLL is different from 1.

out of 1 and 2, which PLL is better for digital modulation schemes.

Thanks
aizzaahmed


On Fri, 07 Oct 2011 11:43:58 -0700, aizza ahmed wrote:

> Hello Everybody, > Thanks to all experts, i am learning a lot from this group. > after studying good amount of literature, i see that the terminology > Loop Bandwidth is more applicable to Analog PLL. Say in Costal PLL, the > more accurate terminologies are Cut-Off frequency of the LPFs and the > quiescient frequency of the NCO. kindly confirm ??
Timing recovery loops (of which the Costas loop is one) depend on features of the data to get information about the clock. In the most basic implementation (which is what you usually see in analog, but works as well in digital-land) the controller (your low pass filters) and oscillator are time invariant and linear. This leads to the "bandwidth" of the loop being data dependent. In the easiest example, BPSK, the only time that there is timing information is when the phase switches -- i.e., when the actual modulating stream switches from a 0 to a 1 or visa versa. So the average loop gain changes with data -- if the raw modulation is 0,1,0,1,0,1 then the loop gain is at its maximum, while if the raw modulation is unchanging then the loop gain is zero. This leads to requirements in most PSK systems that -- however it is accomplished -- the data is bit- stuffed in such a way that the raw modulation sees some minimum rate of transitions so the loop can get traction. This makes stability and performance analysis more complicated -- you basically have to make sure that the system is stable for any allowed data stream that may come your way. It also makes the term "loop bandwidth" meaningless.
> Also i see in matlab simulations on central file exchange, there are two > sets of simulations > > 1. with the Loop Bandwidth, alpha,zeta, c1 and c2 factors. what is this > PLL called and where and how it is used in digital modulation schemes > like bpsk,qpsk and others. > 2. plain 3 LPF + NCO based PLL. what is this PLL called and how it is > used in qpsk,bpsk and others and how this PLL is different from 1. > > out of 1 and 2, which PLL is better for digital modulation schemes.
Please provide links to what you are talking about. -- www.wescottdesign.com
On Oct 7, 4:32&#2013266080;pm, Tim Wescott <t...@seemywebsite.com> wrote:
> > In the easiest example, BPSK, the only time that there is timing > information is when the phase switches -- i.e., when the actual > modulating stream switches from a 0 to a 1 or visa versa. &#2013266080;So the average > loop gain changes with data -- if the raw modulation is 0,1,0,1,0,1 then > the loop gain is at its maximum, while if the raw modulation is > unchanging then the loop gain is zero. &#2013266080;This leads to requirements in > most PSK systems that -- however it is accomplished -- the data is bit- > stuffed in such a way that the raw modulation sees some minimum rate of > transitions so the loop can get traction. >
can they do that, Tim, by using differential coding of the data and simply adding in a timing bit, say one of odd-parity with the remaining bits of a word or frame? that way, if all of the data in the frame is 0 (which means no transitions from 0 to 1 or back), the parity is 1 and you get at least 1 edge per frame in any case. still dunno how you would line up the frame. r b-j
On Fri, 07 Oct 2011 19:24:06 -0700, robert bristow-johnson wrote:

> On Oct 7, 4:32&nbsp;pm, Tim Wescott <t...@seemywebsite.com> wrote: >> >> In the easiest example, BPSK, the only time that there is timing >> information is when the phase switches -- i.e., when the actual >> modulating stream switches from a 0 to a 1 or visa versa. &nbsp;So the >> average loop gain changes with data -- if the raw modulation is >> 0,1,0,1,0,1 then the loop gain is at its maximum, while if the raw >> modulation is unchanging then the loop gain is zero. &nbsp;This leads to >> requirements in most PSK systems that -- however it is accomplished -- >> the data is bit- stuffed in such a way that the raw modulation sees >> some minimum rate of transitions so the loop can get traction. >> >> > can they do that, Tim, by using differential coding of the data and > simply adding in a timing bit, say one of odd-parity with the remaining > bits of a word or frame? that way, if all of the data in the frame is 0 > (which means no transitions from 0 to 1 or back), the parity is 1 and > you get at least 1 edge per frame in any case. still dunno how you > would line up the frame.
Framing is another issue -- most of the protocols I've seen use a unique flag, either all ones or a 1010101 pattern, and have a method of bit stuffing if that flag occurs in the data. One nice way to insure enough ones is to use a FEC protocol that does so -- in fact, IEEE-1394 and (I think) Ethernet use a FEC protocol that codes each byte into 10 bits in such a way that the DC content of the resulting signal is 0, allowing it to be AC coupled. -- www.wescottdesign.com
On Oct 8, 9:15&#2013266080;am, Tim Wescott <t...@seemywebsite.com> wrote:
> On Fri, 07 Oct 2011 19:24:06 -0700, robert bristow-johnson wrote: > > On Oct 7, 4:32&#2013266080;pm, Tim Wescott <t...@seemywebsite.com> wrote: > > >> In the easiest example, BPSK, the only time that there is timing > >> information is when the phase switches -- i.e., when the actual > >> modulating stream switches from a 0 to a 1 or visa versa. &#2013266080;So the > >> average loop gain changes with data -- if the raw modulation is > >> 0,1,0,1,0,1 then the loop gain is at its maximum, while if the raw > >> modulation is unchanging then the loop gain is zero. &#2013266080;This leads to > >> requirements in most PSK systems that -- however it is accomplished -- > >> the data is bit- stuffed in such a way that the raw modulation sees > >> some minimum rate of transitions so the loop can get traction. > > > can they do that, Tim, by using differential coding of the data and > > simply adding in a timing bit, say one of odd-parity with the remaining > > bits of a word or frame? &#2013266080;that way, if all of the data in the frame is 0 > > (which means no transitions from 0 to 1 or back), the parity is 1 and > > you get at least 1 edge per frame in any case. &#2013266080;still dunno how you > > would line up the frame. > > Framing is another issue -- most of the protocols I've seen use a unique > flag, either all ones or a 1010101 pattern, and have a method of bit > stuffing if that flag occurs in the data. > > One nice way to insure enough ones is to use a FEC protocol that does so > -- in fact, IEEE-1394 and (I think) Ethernet use a FEC protocol that > codes each byte into 10 bits in such a way that the DC content of the > resulting signal is 0, allowing it to be AC coupled. > > --www.wescottdesign.com
Thanks Sir for replying, here is the link which i am talking about.. / ========================================================================== if you look at this link, he talks purely in terms of loop bandwidth, alpha, beta,k1 and k2 and http://wenku.baidu.com/view/55f83d270722192e4536f6f5.html http://read.pudn.com/downloads99/sourcecode/app/404855/cotas_carrier_recovery.m__.htm =========================================================================== the second one which i am talking about is this link wherein he talks purely about LPF cutoff frequency, NCO, quiscient frequency and others This is SIMULINK file http://www.mathworks.ch/matlabcentral/fileexchange/16744-demodulating-a-bpsk-using-costas-loop www.sites.google.com/site/santoshjnt/3516a757.pdf the pdf file is the reference for above SIMULINK file ========================================================================================== apart from these, many literature talks .interestingly one doesn't touch others..i mean say a first set of literature doesnt tlak about second nor the second set of persons talk about first set of literature. kindly explain, what is the difference between them Thanks aizza ahmed
On Oct 7, 4:32&#2013266080;pm, Tim Wescott <t...@seemywebsite.com> wrote:

> > In the easiest example, BPSK, the only time that there is timing > information is when the phase switches -- i.e., when the actual > modulating stream switches from a 0 to a 1 or visa versa. &#2013266080;
Or, if one uses split-phase Manchester coding (effectively a (2,1) code), there is a phase switch in every bit interval (guaranteed 100% :-) ) but the signal bandwidth is twice as large. You gets what you pays for....
On Fri, 7 Oct 2011 19:24:06 -0700 (PDT), robert bristow-johnson
<rbj@audioimagination.com> wrote:

>On Oct 7, 4:32=A0pm, Tim Wescott <t...@seemywebsite.com> wrote: >> >> In the easiest example, BPSK, the only time that there is timing >> information is when the phase switches -- i.e., when the actual >> modulating stream switches from a 0 to a 1 or visa versa. =A0So the avera= >ge >> loop gain changes with data -- if the raw modulation is 0,1,0,1,0,1 then >> the loop gain is at its maximum, while if the raw modulation is >> unchanging then the loop gain is zero. =A0This leads to requirements in >> most PSK systems that -- however it is accomplished -- the data is bit- >> stuffed in such a way that the raw modulation sees some minimum rate of >> transitions so the loop can get traction. >> > >can they do that, Tim, by using differential coding of the data and >simply adding in a timing bit, say one of odd-parity with the >remaining bits of a word or frame? that way, if all of the data in >the frame is 0 (which means no transitions from 0 to 1 or back), the >parity is 1 and you get at least 1 edge per frame in any case. still >dunno how you would line up the frame. > >r b-j
It's usually done with a scrambler, which is just an LFSR that is easily invertible. The overhead is zero and there's only one pathological input case, where the input pattern exactly matches the scrambling sequence, where there won't be a nice transition density at the output. Eric Jacobsen Anchor Hill Communications www.anchorhill.com
Tim Wescott <tim@seemywebsite.com> wrote:

(snip)
> One nice way to insure enough ones is to use a FEC protocol that does so > -- in fact, IEEE-1394 and (I think) Ethernet use a FEC protocol that > codes each byte into 10 bits in such a way that the DC content of the > resulting signal is 0, allowing it to be AC coupled.
10baseT uses Manchester coding, naturally allowing for AC coupling. 100baseTX uses 4B/5B coding and then MLT-3. I forget how the bit balance works for 4B/5B, but MLT-3 will also do it. MLT-3 takes the bits, and either changes state (for a one) or not (for a zero). The successive states are (+, 0, -, 0) in a cycle. The result of MLT-3 is that the prinicple frequency component is at one fourth the transition rate, which is 125MHz. Note the exchange of bandwidth for signal/noise requirements. Gigabit ethernet uses 8B/10B coding, which takes 8 data bits and converts them to 10 code bits. The codes either have an equal number of ones and zeros (five each), or six and four. Each of the 256 data groups maps to either a five/five code or a six/four code and its complement. The transmitter keeps a running (one bit) tally of whether there are more ones or zeros. When a six/four code is needed, the appropriate one is chosen based on the tally, and the tally bit is inverted. That is then used directly for optical fiber based gigabit ethernet. 1000baseT (UTP) has a more complicated code, and is then distributed across four UTP pairs. (In each direction at the same time.) A more complicated than MLT-3 line code is used to keep the bandwidth requirements down even more. Adaptive echo cancelation is required, especially with the high attenuation at the higher frequencies. -- glen
On Oct 8, 7:43&#2013266080;am, aizza ahmed <aizzaah...@gmail.com> wrote:
> Hello Everybody, > &#2013266080; &#2013266080; &#2013266080; &#2013266080; &#2013266080;Thanks to all experts, i am learning a lot from this group. > after studying good amount of literature, i see that the terminology > Loop Bandwidth is more applicable to Analog PLL. Say in Costal PLL, > the more accurate terminologies are Cut-Off frequency of the LPFs and > the quiescient frequency of the NCO. kindly confirm ?? >
No. A PLL is a feedback control loop and you must be aware of the unity gain crossover frequency and phase margin. (analogue or digital - makes no difference). it is true that some PLLs require a low bandwidth and others a higher bandwidth, but in both cases you need to be able to stablise the loop.