PLL - quadrature output

Hi

        Does PLL have a property that under locked state, the
output is in quadrature with the reference input ?
I know that this is true if the phase detector is of multiplier/mixer type
( using the approximation  
sin E ~ E  
for error E. )

I am asking whether the above property is there for all plls. If yes, 
why ??

           thanks
              shankar

On 23 Dec 2003 21:43:25 -0800, kbc32@yahoo.com (kbc) wrote:

>Hi
>
>        Does PLL have a property that under locked state, the
>output is in quadrature with the reference input ?
>I know that this is true if the phase detector is of multiplier/mixer type
>( using the approximation  
>sin E ~ E  
>for error E. )
>
>I am asking whether the above property is there for all plls. If yes, 
>why ??

No, it is not true for all PLLs, as the lock point depends on the type
of phase detector and the loop filter.

There are two cases to consider for the loop filter:

a)  A type 1 PLL won't have an integrating term in the loop filter.
At lock, the phase between the input and output will vary with the
frequency difference between the input and the free running VCO
frequency.

b) A type 2 (or higher) PLL has at least one integrator in the loop
filter.  At lock, the average output of the phase detector must not
cause the integrator to ramp.

Also think about the effects of leakage currents and opamp offset
voltages - there will need to be some steady state phase difference at
the pd input to account for these.


There are also different sorts of phase detectors.  Some produce
"zero" output when there is a pi/2 difference in the input phases
(such as the XOR gate).  Others produce "zero" output when the inputs
are in phase (such as most edge triggered phase detectors).

AFAIK, *all* PFDs (phase and frequency detectors) used in modern
frequency synthesiser devices are edge triggered, and the inputs will
be in phase when locked.

Regards,
Allan.

kbc wrote:

> Hi
>
>         Does PLL have a property that under locked state, the
> output is in quadrature with the reference input ?
> I know that this is true if the phase detector is of multiplier/mixer type
> ( using the approximation
> sin E ~ E
> for error E. )
>
> I am asking whether the above property is there for all plls. If yes,
> why ??
>
>            thanks
>               shankar

Not sure about all PLLs but simply if in quadrature if we have cos(x) and
sin(x) then if you multiply and integrate you get zero ie when in lock the
error is zero in theory at least. In practise this depends on the bandwidth of
the loop and what frequency is being prevented etc.Of course the error can
never be exactly zero - like an op-amp there has to be some error to make it
work.

Tom

Allan Herriman wrote:

> On 23 Dec 2003 21:43:25 -0800, kbc32@yahoo.com (kbc) wrote:
>
> >Hi
> >
> >        Does PLL have a property that under locked state, the
> >output is in quadrature with the reference input ?
> >I know that this is true if the phase detector is of multiplier/mixer type
> >( using the approximation
> >sin E ~ E
> >for error E. )
> >
> >I am asking whether the above property is there for all plls. If yes,
> >why ??
>
> No, it is not true for all PLLs, as the lock point depends on the type
> of phase detector and the loop filter.
>
> There are two cases to consider for the loop filter:
>
> a)  A type 1 PLL won't have an integrating term in the loop filter.
> At lock, the phase between the input and output will vary with the
> frequency difference between the input and the free running VCO
> frequency.
>

Normally a type 1 system is defined (in control theory books) as a system with
at least one pure  integrator so a type 1 PLL would have
 only the VCO (the 'pure' integrator) + some other filter dynamics - say a low
pass filter or whatever.

>
> b) A type 2 (or higher) PLL has at least one integrator in the loop
> filter.  At lock, the average output of the phase detector must not
> cause the integrator to ramp.
>

A type 2 would be the VCO + an added integrator + phase advance
compensation.(ie two pure integrators+compensation)

Not sure I agree entirely with your analogy. All servos should have as many
integrators as possible (normally no more than two + compensation). Having a
type 1 is like having a poorly compensated loop - ie we can do more
to make it track better by adding a second integrator (or a lag-lead). Clearly
so-called PID control could well be PI^2D control ie two integrators are always
better than one!
Of course in the time-domain there are differences as you point out. I expect
you mean that with one integrator we can track step inputs with theoretically
zero error and for type II we can track a ramping input with zero error.


Tom

On Fri, 09 Jan 2004 20:43:15 +1300, Tom <somebody@nOpam.com> wrote:

>
>
>Allan Herriman wrote:
>
>> On 23 Dec 2003 21:43:25 -0800, kbc32@yahoo.com (kbc) wrote:
>>
>> >Hi
>> >
>> >        Does PLL have a property that under locked state, the
>> >output is in quadrature with the reference input ?
>> >I know that this is true if the phase detector is of multiplier/mixer type
>> >( using the approximation
>> >sin E ~ E
>> >for error E. )
>> >
>> >I am asking whether the above property is there for all plls. If yes,
>> >why ??
>>
>> No, it is not true for all PLLs, as the lock point depends on the type
>> of phase detector and the loop filter.
>>
>> There are two cases to consider for the loop filter:
>>
>> a)  A type 1 PLL won't have an integrating term in the loop filter.
>> At lock, the phase between the input and output will vary with the
>> frequency difference between the input and the free running VCO
>> frequency.
>>
>
>Normally a type 1 system is defined (in control theory books) as a system with
>at least one pure  integrator so a type 1 PLL would have
> only the VCO (the 'pure' integrator) + some other filter dynamics - say a low
>pass filter or whatever.

I think that should be "exactly one pure integrator" rather than "at
least one pure integrator" as that is the definition of a type 1
system.  (At least, that's how the term was defined when I went to
school.)

Note that when using the commonly accepted nomenclature, the
integrator due to the VCO is not regarded as part of the loop filter
in a PLL.  It's part of the *loop*, but not the *loop filter*.
I refer you to any of the standard PLL texts (e.g. Gardiner).

So a type 1 system has exactly one pure integrator (the VCO) and the
loop filter has no pure integrators (which is what we both said).

>> b) A type 2 (or higher) PLL has at least one integrator in the loop
>> filter.  At lock, the average output of the phase detector must not
>> cause the integrator to ramp.
>>
>
>A type 2 would be the VCO + an added integrator + phase advance
>compensation.(ie two pure integrators+compensation)
>
>Not sure I agree entirely with your analogy. 

I wasn't aware I was making an analogy.  The type 2 PLL has exactly
one pure integrator in the loop filter and another pure integrator in
the form of the VCO.  Higher order PLLs will have more integrators in
the loop filter.  This comes straight from the definition of the
"type".

There will also be a compensating zero in the loop filter, as you
point out, but this isn't relevant to the definition of the type, nor
to the steady state phase error (except in that it is needed to make
the loop stable, and without that there is no steady state phase
error).

>All servos should have as many
>integrators as possible (normally no more than two + compensation). Having a
>type 1 is like having a poorly compensated loop - ie we can do more
>to make it track better by adding a second integrator (or a lag-lead). Clearly
>so-called PID control could well be PI^2D control ie two integrators are always
>better than one!

I wasn't claiming that type 1 systems were good in general.  However,
they do exist (and may be a good choice in certain PLL applications),
and this has an important implication for the steady state phase error
when in lock (which is pertinent to the OP's question).

>Of course in the time-domain there are differences as you point out. I expect
>you mean that with one integrator we can track step inputs with theoretically
>zero error and for type II we can track a ramping input with zero error.

Yes.  These are all results from an introductory control theory
course.
[ I assume that when you say "with one integrator" you are referring
to the one in the VCO, i.e. the loop filter doesn't contain a pure
integrator. ]

Note also that these steps and ramps refer to *phase*.  A steadily
ramping phase is the same thing as a frequency offset.
Our type II loop allows us to have zero steady state phase error in
response to a frequency step, which is a common requirement for many
PLLs.

A frequency step is one of the commonest tests for a PLL, perhaps
because it is usually easy to do (by "changing channels").

Regards,
Allan.