Polyphase Filter

Started by mishrask March 18, 2012
Hi ,
    I am designing a polyphase filter in HW, which will do a sample rate
upconversion by a factor of 1.25 on the incoming data.It is implemented as
a upsampling by 5 followed by a decimation(polyphase)by 4(5/4=1.25)...For
this design let's say I have a clock rate of 100kHz then I am not sure what
will be the maximum limit on the input data sampling rate(Fs_input) which
my design can handle ....Please answer the Question if  
 
                 CASE1. I have a FIFO to store incoming data in my design
[in this case please elaborate on the relation between the burst rate of
incoming data and size of the FIFO i.e. say I have a input sampling rate of
2kHz and source is sending in a way that it sends the data continuously for
4k cycles and then keeps quiet for next 100k*2-4k cycles => 4ksamples in 2
secs ,so avg sampling rate =2k samples /sec]
                 CASE2.I don't have any internal storage in my design 

please , help me understand it ..

Reagrds,
SKM


On Sun, 18 Mar 2012 12:35:24 -0500, mishrask wrote:

> Hi , > I am designing a polyphase filter in HW, which will do a sample rate > upconversion by a factor of 1.25 on the incoming data.It is implemented > as a upsampling by 5 followed by a decimation(polyphase)by > 4(5/4=1.25)...For this design let's say I have a clock rate of 100kHz > then I am not sure what will be the maximum limit on the input data > sampling rate(Fs_input) which my design can handle ....Please answer the > Question if > > CASE1. I have a FIFO to store incoming data in my > design > [in this case please elaborate on the relation between the burst rate of > incoming data and size of the FIFO i.e. say I have a input sampling rate > of 2kHz and source is sending in a way that it sends the data > continuously for 4k cycles and then keeps quiet for next 100k*2-4k > cycles => 4ksamples in 2 secs ,so avg sampling rate =2k samples /sec] > CASE2.I don't have any internal storage in my design > > please , help me understand it .. > > Reagrds, > SKM
This sounds suspiciously homework-ish. It's the totally unrelated case 1 and case 2... Why do you want to waste cycles by upsampling when you don't have to? Why not do a true polyphase filter with five kernels (I assume you're doing this as a FIR), and with the appropriate one selected for each output phase? The maximum input on your sampling rate depends on your clock rate _and_ what you can do with it. If you don't limit the amount of logic, then your throughput is also pretty close to unbounded, but sampling out at faster than 100kHz would get inconvenient. So for both cited cases, your input sampling rate is "limited" to 80kHz. -- Tim Wescott Control system and signal processing consulting www.wescottdesign.com
On 3/18/2012 10:35 AM, mishrask wrote:
> say I have a input sampling rate of > 2kHz and source is sending in a way that it sends the data continuously for > 4k cycles and then keeps quiet for next 100k*2-4k cycles => 4ksamples in 2 > secs ,so avg sampling rate =2k samples /sec]
I understand the intent but not this description. Input sample rate (of something) at 2kHz. OK. That seems clear enough. Data is received at some rate in 4K sample blocks??? No data for 196,000 sample periods? (this would be equivalent to 98 seconds 196,000/2,000). Or, maybe you mean there are 4k samples every 200,000 periods or every 100 seconds? Same thing I guess. 4k samples in 2 seconds is, yes, 2ksps. What are your objectives? Do you want to process the data in a streaming sense at 4ks/100 sec = 40 samples/second? Or what? Presumably you can process as fast as you like. So this means a buffer of 4ks less the processing rate, eh? That is, if you can only process at 1ks/sec then at then end of 4ks in 2 sec you'd have only processed 2ks and need a 2ks buffer. If the processing rate is 2ks/sec then no buffer is needed other than an input register which I wouldn't exactly call a buffer. Fred
>On Sun, 18 Mar 2012 12:35:24 -0500, mishrask wrote: > >> Hi , >> I am designing a polyphase filter in HW, which will do a sample
rate
>> upconversion by a factor of 1.25 on the incoming data.It is implemented >> as a upsampling by 5 followed by a decimation(polyphase)by >> 4(5/4=1.25)...For this design let's say I have a clock rate of 100kHz >> then I am not sure what will be the maximum limit on the input data >> sampling rate(Fs_input) which my design can handle ....Please answer
the
>> Question if >> >> CASE1. I have a FIFO to store incoming data in my >> design >> [in this case please elaborate on the relation between the burst rate
of
>> incoming data and size of the FIFO i.e. say I have a input sampling
rate
>> of 2kHz and source is sending in a way that it sends the data >> continuously for 4k cycles and then keeps quiet for next 100k*2-4k >> cycles => 4ksamples in 2 secs ,so avg sampling rate =2k samples /sec] >> CASE2.I don't have any internal storage in my design >> >> please , help me understand it .. >> >> Reagrds, >> SKM > >This sounds suspiciously homework-ish. It's the totally unrelated case 1
>and case 2... > >Why do you want to waste cycles by upsampling when you don't have to? >Why not do a true polyphase filter with five kernels (I assume you're >doing this as a FIR), and with the appropriate one selected for each >output phase? > >The maximum input on your sampling rate depends on your clock rate _and_ >what you can do with it. If you don't limit the amount of logic, then >your throughput is also pretty close to unbounded, but sampling out at >faster than 100kHz would get inconvenient. So for both cited cases, your
>input sampling rate is "limited" to 80kHz. > >-- >Tim Wescott >Control system and signal processing consulting >www.wescottdesign.com >
Hi Tim , Ya,you are right ..I am doing it just for learning purpose(implementation in Matlab and Verilog-HW).. It seems I didn't make it clear in my previous post ... My goal is to achieve a up-sampling by 1.25 ...which I am doing as up-sampling by 5[i.e 4-zeros stuffing] followed by polyphase decimation by 4 ...Now my design has to work for any sampling rate less than 80Mhz if my clock is 100Mhz ,correct.But let's consider a sampling rate of 30Mhz ...The device which is sending data to my filter may achieve this rate (wrt clock) as it wishes , i.e. for 30M samples in 100M clock cycles it can send in any fashion ...it will send it for first 30M clock cycles and then will keep silent for next 70M clock cycles or can send samples for 15M clock cycles wait for next 70 clocks and then send rest 15M samples or in any fashion u can imagine, maintaining a over all 30M samples in 100 clock cycles [i.e 30Msamples/sec]...now to stuff 4 zeros between the samples [up-sampling by 5] I need 4 extra clocks per sample ...But if my input sampling rate is too high (close to 80MHz)I need to have an internal storage(FiFo) to store incoming data , so that while I am zero-stuffing[i.e taking 4 extra clocks ] I don't miss any input sample.....Hope it makes it clear...I am worried about the relation between size of the FIFO and the way data is being sent to the Filter.. few Qs regarding your post... 1.By your method [Why not do a true polyphase filter with five kernels ]...Do you mean that I should do a polyphase upsampling by 5 and then discard each 4th sample...else how I will achieve 1.25 (fractional) upsampling ?? 2.how suitable is polynomial interpolation in such a case ?? Regards Sujeet
On Wed, 21 Mar 2012 08:06:24 -0500, mishrask wrote:

>>On Sun, 18 Mar 2012 12:35:24 -0500, mishrask wrote: >> >>> Hi , >>> I am designing a polyphase filter in HW, which will do a sample > rate >>> upconversion by a factor of 1.25 on the incoming data.It is >>> implemented as a upsampling by 5 followed by a decimation(polyphase)by >>> 4(5/4=1.25)...For this design let's say I have a clock rate of 100kHz >>> then I am not sure what will be the maximum limit on the input data >>> sampling rate(Fs_input) which my design can handle ....Please answer > the >>> Question if >>> >>> CASE1. I have a FIFO to store incoming data in my >>> design >>> [in this case please elaborate on the relation between the burst rate > of >>> incoming data and size of the FIFO i.e. say I have a input sampling > rate >>> of 2kHz and source is sending in a way that it sends the data >>> continuously for 4k cycles and then keeps quiet for next 100k*2-4k >>> cycles => 4ksamples in 2 secs ,so avg sampling rate =2k samples /sec] >>> CASE2.I don't have any internal storage in my design >>> >>> please , help me understand it .. >>> >>> Reagrds, >>> SKM >> >>This sounds suspiciously homework-ish. It's the totally unrelated case >>1 > >>and case 2... >> >>Why do you want to waste cycles by upsampling when you don't have to? >>Why not do a true polyphase filter with five kernels (I assume you're >>doing this as a FIR), and with the appropriate one selected for each >>output phase? >> >>The maximum input on your sampling rate depends on your clock rate _and_ >>what you can do with it. If you don't limit the amount of logic, then >>your throughput is also pretty close to unbounded, but sampling out at >>faster than 100kHz would get inconvenient. So for both cited cases, >>your > >>input sampling rate is "limited" to 80kHz. >> >>-- >>Tim Wescott >>Control system and signal processing consulting www.wescottdesign.com >> >> > Hi Tim , > Ya,you are right ..I am doing it just for learning > purpose(implementation in Matlab and Verilog-HW).. > It seems I didn't make it clear in my previous post ... > My goal is to achieve a up-sampling by 1.25 ...which I am doing as > up-sampling by 5[i.e 4-zeros stuffing] followed by polyphase decimation > by 4 ...Now my design has to work for any sampling rate less than 80Mhz > if my clock is 100Mhz ,correct.But let's consider a sampling rate of > 30Mhz ...The device which is sending data to my filter may achieve this > rate (wrt clock) as it wishes , i.e. for 30M samples in 100M clock > cycles it can send in any fashion ...it will send it for first 30M clock > cycles and then will keep silent for next 70M clock cycles or can send > samples for 15M clock cycles wait for next 70 clocks and then send rest > 15M samples or in any fashion u can imagine, maintaining a over all 30M > samples in 100 clock cycles [i.e 30Msamples/sec]...now to stuff 4 zeros > between the samples [up-sampling by 5] I need 4 extra clocks per sample > ...But if my input sampling rate is too high (close to 80MHz)I need to > have an internal storage(FiFo) to store incoming data , so that while I > am zero-stuffing[i.e taking 4 extra clocks ] I don't miss any input > sample.....Hope it makes it clear...I am worried about the relation > between size of the FIFO and the way data is being sent to the Filter.. > > few Qs regarding your post... > 1.By your method [Why not do a true polyphase filter with five kernels > ]...Do you mean that I should do a polyphase upsampling by 5 and then > discard each 4th sample...else how I will achieve 1.25 (fractional) > upsampling ?? > > 2.how suitable is polynomial interpolation in such a case ??
I understood your original post perfectly. Instead of running an N/4 tap filter at 1.25 * f_in, you want to run an N tap filter at 5*f_in. I, for one, don't see the advantage of doing 20 times the processing that you need just so you don't have to turn to the second half of the first chapter of your book on multirate processing. -- Tim Wescott Control system and signal processing consulting www.wescottdesign.com