interpolator

On 4/2/12 9:39 PM, mishrask wrote:
>          This is not a public document but still I will try to put as much
> details as i can here .But my focus was on something else ..I have to
> implement it in hardware (Verilog,it's part of an ASIC).

sounds like you will want to minimize the number of coefficients.  do 
you have MIPS to burn with your ASIC?  (probably not.)

> I request you and
> others also to please try to answer my ignored Qs ----

i sorta ignore Qs that i dunno what they mean.  thems are hard questions.


> "and one more question --- can someone please elaborate on the clock
> requirements in a sample rate converter with a suitable example [sampling
> rate and clock rates say for SRC by factor of 1.3564]

are you asking how to derive the output clock, given an input clock and 
an SRC ratio?  you need to have a very high frequency constant clock 
that you can divide off of with a counter.

if it's an ASRC ("A" for "asynchronous"), then you are given two clocks, 
one for the input samples and one for the output and you have to derive 
the SRC ratio from that.  this requires a servo-control mechanism like 
we learned in our control systems classes besides some other techniques.

> (I didn't get any
> reference about this ,so please give if you know.The books I have referred
> to are dsp books and they don't at all talk about the clock rates) ....
> Lets' say I have a single clock in my design ,then  do I need to divide
> the clock and use different clocks for i/p and o/p (in this case how to go
> about for like SRC by 1.765 factor)...or some other way is there ."

you still need to decide how you're getting that 1.765 factor.  from two 
different clocks?  or is that a constant parameter, and you need to 
derive an output clock from that parameter (and the input clock)?

can't help you much more without this getting thought out (by you).

-- 

r b-j                  rbj@audioimagination.com

"Imagination is more important than knowledge."