Hi Guys, I've been trying to learn about those darned cascaded integrator-comb (CIC) filters and have reviewed Hogenaurer's original paper Hogenauer, E. "An Economical Class of Digital Filters For Decimation and Interpolation," IEEE Trans. Acoust. Speech and Signal Proc., Vol. ASSP?29, pp. 155-162, April 1981. and Matt Donadio's CIC write-up (on www.dspguru.com). But I ran into something concerning CIC interpolators that I don't understand and hope you folk might help me out. Hogenauer says (on pp. 160) that there will be bit growth (gain) through the interpolator's comb filter(s) (differentiators) comprising the initial stage(s) of a CIC interpolation filter. He says the bit growth will be a factor of 2 for each comb filter used in the implementation. Because a comb (differentiator) merely outputs the difference between successive inputs, I don't see how there can be bit growth (gain) through the comb stages. My MATLAB modeling shows no gain (bit growth) in the interpolator's comb filters. They have a gain of zero at DC. (My modeling agrees with what Ray Andraka has stated here, for the gain of a CIC interpolator, several times on this newsgroup.) Anyway, my questions are: is there really bit growth (gain) in the initial comb stages of a CIC interpolation filter? Am I missing something simple here? Do I need to increase the dosage of my medication? Thanks for any help, [-Rick-]

# Cascaded integrator-comb (CIC) filter question

Rick Lyons wrote:> > Hi Guys, > > I've been trying to learn about those darned cascaded > integrator-comb (CIC) filters and have reviewed > Hogenaurer's original paper > > Hogenauer, E. "An Economical Class of Digital Filters > For Decimation and Interpolation," IEEE Trans. Acoust. > Speech and Signal Proc., Vol. ASSP?29, pp. 155-162, > April 1981. > > and Matt Donadio's CIC write-up (on www.dspguru.com). > > But I ran into something concerning CIC interpolators > that I don't understand and hope you folk might help > me out. > > Hogenauer says (on pp. 160) that there will be bit growth > (gain) through the interpolator's comb filter(s) > (differentiators) comprising the initial stage(s) > of a CIC interpolation filter. He says the bit > growth will be a factor of 2 > for each comb filter used in the implementation. > Because a comb (differentiator) merely outputs > the difference between successive inputs, I don't see > how there can be bit growth (gain) through the comb > stages.The frequency response for a filter [1 -1] is a sin function with a gain of 2 at fs/2 (i.e. Pi/2). Consider the sequence 1 -1 1 -1 1 -1 ...... What would be the output after putting that thru the differentiator. Of course in real life a signal usually won't have that much energy near fs/2, so the issue of 'bit growth' (or overflow) may not be observed. -jim -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 100,000 Newsgroups - 19 Different Servers! =-----

I designed a CIC in VHDL for Altera for our 1 Gs/s ADC. I just parameterised everything, and used an example from literature to test the design. I am not an expert in choosing the bit widths. The comb filters just keeps accumulating samples. The accumulation result gets bigger and bigger. If you subsample with a factor 16, the accumulation register should not overflow within that period. I chose a wrong width ones and did notice wrong results at the output. regards, -- Peter Beukelman senior ASIC designer http://www.eonic.com "Rick Lyons" <ricklyon@REMOVE.onemain.com> wrote in message news:3f402ef6.115258812@news.west.earthlink.net...> > Hi Guys, > > I've been trying to learn about those darned cascaded > integrator-comb (CIC) filters and have reviewed > Hogenaurer's original paper > > Hogenauer, E. "An Economical Class of Digital Filters > For Decimation and Interpolation," IEEE Trans. Acoust. > Speech and Signal Proc., Vol. ASSP?29, pp. 155-162, > April 1981. > > and Matt Donadio's CIC write-up (on www.dspguru.com). > > But I ran into something concerning CIC interpolators > that I don't understand and hope you folk might help > me out. > > Hogenauer says (on pp. 160) that there will be bit growth > (gain) through the interpolator's comb filter(s) > (differentiators) comprising the initial stage(s) > of a CIC interpolation filter. He says the bit > growth will be a factor of 2 > for each comb filter used in the implementation. > Because a comb (differentiator) merely outputs > the difference between successive inputs, I don't see > how there can be bit growth (gain) through the comb > stages. > > My MATLAB modeling shows no gain (bit growth) in the > interpolator's comb filters. They have a gain of zero > at DC. (My modeling agrees with what Ray Andraka has > stated here, for the gain of a CIC interpolator, > several times on this newsgroup.) > > Anyway, my questions are: is there really bit > growth (gain) in the initial comb stages of a CIC > interpolation filter? Am I missing something simple > here? Do I need to increase the dosage of my medication? > > Thanks for any help, > [-Rick-] > >

On Mon, 18 Aug 2003 06:20:25 -0500, jim <sjedging@mwt.net> wrote:> > >Rick Lyons wrote: >> >> Hi Guys, >> >> I've been trying to learn about those darned cascaded >> integrator-comb (CIC) filters and have reviewed >> Hogenaurer's original paper >> >> Hogenauer, E. "An Economical Class of Digital Filters >> For Decimation and Interpolation," IEEE Trans. Acoust. >> Speech and Signal Proc., Vol. ASSP?29, pp. 155-162, >> April 1981. >> >> and Matt Donadio's CIC write-up (on www.dspguru.com). >> >> But I ran into something concerning CIC interpolators >> that I don't understand and hope you folk might help >> me out. >> >> Hogenauer says (on pp. 160) that there will be bit growth >> (gain) through the interpolator's comb filter(s) >> (differentiators) comprising the initial stage(s) >> of a CIC interpolation filter. He says the bit >> growth will be a factor of 2 >> for each comb filter used in the implementation. >> Because a comb (differentiator) merely outputs >> the difference between successive inputs, I don't see >> how there can be bit growth (gain) through the comb >> stages. > >The frequency response for a filter [1 -1] is a sin function with a gain >of 2 at fs/2 (i.e. Pi/2). Consider the sequence 1 -1 1 -1 1 -1 ...... What >would be the output after putting that thru the differentiator. > Of course in real life a signal usually won't have that much energy near >fs/2, so the issue of 'bit growth' (or overflow) may not be observed. > >-jimHi Jim, Yes, yes. The peak freq mag response of a comb is two. Darn. Thanks for reminding me. I agree with what you wrote. If the comb has a delay of 2 samples, the gain peak (two) will occur at fs/4. [-Rick-]

Hi Peter, did you really build a 1 Gsample/sec A/D converter?(!!) I don't even want to *think* about it. I mean, how do you 'breadboard' a circuit that runs at 1 GHz. How do you inject test signals? How do you monitor voltages at different nodes? I checked my Radio Shack catalog and they don't even sell test equipment that operates at 1 GHz. [-Rick-] ------------------------------------------- On Mon, 18 Aug 2003 13:32:28 +0200, "John Smith" <piet@bel.com> wrote:>I designed a CIC in VHDL for Altera for our 1 Gs/s ADC. I just parameterised >everything, and used an example from literature to test the design. I am not >an expert in choosing the bit widths. >The comb filters just keeps accumulating samples. The accumulation result >gets bigger and bigger. If you subsample with a factor 16, the accumulation >register should not overflow within that period. I chose a wrong width ones >and did notice wrong results at the output. >regards, >-- >Peter Beukelman >senior ASIC designer >http://www.eonic.com >"Rick Lyons" <ricklyon@REMOVE.onemain.com> wrote in message >news:3f402ef6.115258812@news.west.earthlink.net... >> >> Hi Guys, >> >> I've been trying to learn about those darned cascaded >> integrator-comb (CIC) filters and have reviewed >> Hogenaurer's original paper >> >> Hogenauer, E. "An Economical Class of Digital Filters >> For Decimation and Interpolation," IEEE Trans. Acoust. >> Speech and Signal Proc., Vol. ASSP?29, pp. 155-162, >> April 1981. >> >> and Matt Donadio's CIC write-up (on www.dspguru.com). >> >> But I ran into something concerning CIC interpolators >> that I don't understand and hope you folk might help >> me out. >> >> Hogenauer says (on pp. 160) that there will be bit growth >> (gain) through the interpolator's comb filter(s) >> (differentiators) comprising the initial stage(s) >> of a CIC interpolation filter. He says the bit >> growth will be a factor of 2 >> for each comb filter used in the implementation. >> Because a comb (differentiator) merely outputs >> the difference between successive inputs, I don't see >> how there can be bit growth (gain) through the comb >> stages. >> >> My MATLAB modeling shows no gain (bit growth) in the >> interpolator's comb filters. They have a gain of zero >> at DC. (My modeling agrees with what Ray Andraka has >> stated here, for the gain of a CIC interpolator, >> several times on this newsgroup.) >> >> Anyway, my questions are: is there really bit >> growth (gain) in the initial comb stages of a CIC >> interpolation filter? Am I missing something simple >> here? Do I need to increase the dosage of my medication? >> >> Thanks for any help, >> [-Rick-] >> >> > >

Rick, Hotrod ADCs with samples rate >=1Gsps are not unusual these days, at least in labs. I know of at least one 4-bit, 1Gsps monolithic ADC in a lab, and they're working to add two more bits. There are non-monolithic converters that operate in those ranges as well that are commercialized. There may be monolothic converters on the market in that range, too... On Wed, 20 Aug 2003 05:47:57 GMT, ricklyon@REMOVE.onemain.com (Rick Lyons) wrote:> >Hi Peter, > did you really build a 1 Gsample/sec A/D converter?(!!) > >I don't even want to *think* about it. >I mean, how do you 'breadboard' a circuit that >runs at 1 GHz. How do you inject test signals? >How do you monitor voltages at different nodes? >I checked my Radio Shack catalog and they don't >even sell test equipment that operates at 1 GHz. > >[-Rick-] > >------------------------------------------- >On Mon, 18 Aug 2003 13:32:28 +0200, "John Smith" <piet@bel.com> wrote: > >>I designed a CIC in VHDL for Altera for our 1 Gs/s ADC. I just parameterised >>everything, and used an example from literature to test the design. I am not >>an expert in choosing the bit widths. >>The comb filters just keeps accumulating samples. The accumulation result >>gets bigger and bigger. If you subsample with a factor 16, the accumulation >>register should not overflow within that period. I chose a wrong width ones >>and did notice wrong results at the output. >>regards, >>-- >>Peter Beukelman >>senior ASIC designer >>http://www.eonic.com >>"Rick Lyons" <ricklyon@REMOVE.onemain.com> wrote in message >>news:3f402ef6.115258812@news.west.earthlink.net... >>> >>> Hi Guys, >>> >>> I've been trying to learn about those darned cascaded >>> integrator-comb (CIC) filters and have reviewed >>> Hogenaurer's original paper >>> >>> Hogenauer, E. "An Economical Class of Digital Filters >>> For Decimation and Interpolation," IEEE Trans. Acoust. >>> Speech and Signal Proc., Vol. ASSP?29, pp. 155-162, >>> April 1981. >>> >>> and Matt Donadio's CIC write-up (on www.dspguru.com). >>> >>> But I ran into something concerning CIC interpolators >>> that I don't understand and hope you folk might help >>> me out. >>> >>> Hogenauer says (on pp. 160) that there will be bit growth >>> (gain) through the interpolator's comb filter(s) >>> (differentiators) comprising the initial stage(s) >>> of a CIC interpolation filter. He says the bit >>> growth will be a factor of 2 >>> for each comb filter used in the implementation. >>> Because a comb (differentiator) merely outputs >>> the difference between successive inputs, I don't see >>> how there can be bit growth (gain) through the comb >>> stages. >>> >>> My MATLAB modeling shows no gain (bit growth) in the >>> interpolator's comb filters. They have a gain of zero >>> at DC. (My modeling agrees with what Ray Andraka has >>> stated here, for the gain of a CIC interpolator, >>> several times on this newsgroup.) >>> >>> Anyway, my questions are: is there really bit >>> growth (gain) in the initial comb stages of a CIC >>> interpolation filter? Am I missing something simple >>> here? Do I need to increase the dosage of my medication? >>> >>> Thanks for any help, >>> [-Rick-] >>> >>> >> >> >Eric Jacobsen Minister of Algorithms, Intel Corp. My opinions may not be Intel's opinions. http://www.ericjacobsen.org

I did an FFT that worked at 960 MHz a year and a half ago in an FPGA. The application had an Atmel 1GHz 8 bit ADC coupled to the FPGA, and the FPGA did overlapped FFTs on the data in real time. Eric Jacobsen wrote:> Rick, > > Hotrod ADCs with samples rate >=1Gsps are not unusual these days, at > least in labs. I know of at least one 4-bit, 1Gsps monolithic ADC in > a lab, and they're working to add two more bits. There are > non-monolithic converters that operate in those ranges as well that > are commercialized. There may be monolothic converters on the market > in that range, too... > > On Wed, 20 Aug 2003 05:47:57 GMT, ricklyon@REMOVE.onemain.com (Rick > Lyons) wrote: > > > > >Hi Peter, > > did you really build a 1 Gsample/sec A/D converter?(!!) > > > >I don't even want to *think* about it. > >I mean, how do you 'breadboard' a circuit that > >runs at 1 GHz. How do you inject test signals? > >How do you monitor voltages at different nodes? > >I checked my Radio Shack catalog and they don't > >even sell test equipment that operates at 1 GHz. > > > >[-Rick-] > > > >------------------------------------------- > >On Mon, 18 Aug 2003 13:32:28 +0200, "John Smith" <piet@bel.com> wrote: > > > >>I designed a CIC in VHDL for Altera for our 1 Gs/s ADC. I just parameterised > >>everything, and used an example from literature to test the design. I am not > >>an expert in choosing the bit widths. > >>The comb filters just keeps accumulating samples. The accumulation result > >>gets bigger and bigger. If you subsample with a factor 16, the accumulation > >>register should not overflow within that period. I chose a wrong width ones > >>and did notice wrong results at the output. > >>regards, > >>-- > >>Peter Beukelman > >>senior ASIC designer > >>http://www.eonic.com > >>"Rick Lyons" <ricklyon@REMOVE.onemain.com> wrote in message > >>news:3f402ef6.115258812@news.west.earthlink.net... > >>> > >>> Hi Guys, > >>> > >>> I've been trying to learn about those darned cascaded > >>> integrator-comb (CIC) filters and have reviewed > >>> Hogenaurer's original paper > >>> > >>> Hogenauer, E. "An Economical Class of Digital Filters > >>> For Decimation and Interpolation," IEEE Trans. Acoust. > >>> Speech and Signal Proc., Vol. ASSP?29, pp. 155-162, > >>> April 1981. > >>> > >>> and Matt Donadio's CIC write-up (on www.dspguru.com). > >>> > >>> But I ran into something concerning CIC interpolators > >>> that I don't understand and hope you folk might help > >>> me out. > >>> > >>> Hogenauer says (on pp. 160) that there will be bit growth > >>> (gain) through the interpolator's comb filter(s) > >>> (differentiators) comprising the initial stage(s) > >>> of a CIC interpolation filter. He says the bit > >>> growth will be a factor of 2 > >>> for each comb filter used in the implementation. > >>> Because a comb (differentiator) merely outputs > >>> the difference between successive inputs, I don't see > >>> how there can be bit growth (gain) through the comb > >>> stages. > >>> > >>> My MATLAB modeling shows no gain (bit growth) in the > >>> interpolator's comb filters. They have a gain of zero > >>> at DC. (My modeling agrees with what Ray Andraka has > >>> stated here, for the gain of a CIC interpolator, > >>> several times on this newsgroup.) > >>> > >>> Anyway, my questions are: is there really bit > >>> growth (gain) in the initial comb stages of a CIC > >>> interpolation filter? Am I missing something simple > >>> here? Do I need to increase the dosage of my medication? > >>> > >>> Thanks for any help, > >>> [-Rick-] > >>> > >>> > >> > >> > > > > Eric Jacobsen > Minister of Algorithms, Intel Corp. > My opinions may not be Intel's opinions. > http://www.ericjacobsen.org-- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

Rick, the growth in a decimating CIC is in the integrator. The comb can drop one LSB per stage if you don't need the full precision without loss of function. In the interpolating filter, the combs come first, and in that case there is a growth of one bit in each layer of the comb. The comb can't have any overflow or the differences would not accumulate properly in the integrator. An extra bit at each level of the comb ensures that you will never have an overflow in the comb sections. Rick Lyons wrote:> Hi Guys, > > I've been trying to learn about those darned cascaded > integrator-comb (CIC) filters and have reviewed > Hogenaurer's original paper > > Hogenauer, E. "An Economical Class of Digital Filters > For Decimation and Interpolation," IEEE Trans. Acoust. > Speech and Signal Proc., Vol. ASSP?29, pp. 155-162, > April 1981. > > and Matt Donadio's CIC write-up (on www.dspguru.com). > > But I ran into something concerning CIC interpolators > that I don't understand and hope you folk might help > me out. > > Hogenauer says (on pp. 160) that there will be bit growth > (gain) through the interpolator's comb filter(s) > (differentiators) comprising the initial stage(s) > of a CIC interpolation filter. He says the bit > growth will be a factor of 2 > for each comb filter used in the implementation. > Because a comb (differentiator) merely outputs > the difference between successive inputs, I don't see > how there can be bit growth (gain) through the comb > stages. > > My MATLAB modeling shows no gain (bit growth) in the > interpolator's comb filters. They have a gain of zero > at DC. (My modeling agrees with what Ray Andraka has > stated here, for the gain of a CIC interpolator, > several times on this newsgroup.) > > Anyway, my questions are: is there really bit > growth (gain) in the initial comb stages of a CIC > interpolation filter? Am I missing something simple > here? Do I need to increase the dosage of my medication? > > Thanks for any help, > [-Rick-]-- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

Ray, Gnarly. Do you recall how expensive that ADC was or how much power it used? Both parameters are improving quickly these days... On Wed, 27 Aug 2003 20:29:37 -0400, Ray Andraka <ray@andraka.com> wrote:>I did an FFT that worked at 960 MHz a year and a half ago in an FPGA. The >application had an Atmel 1GHz 8 bit ADC coupled to the FPGA, and the FPGA did >overlapped FFTs on the data in real time. > >Eric Jacobsen wrote: > >> Rick, >> >> Hotrod ADCs with samples rate >=1Gsps are not unusual these days, at >> least in labs. I know of at least one 4-bit, 1Gsps monolithic ADC in >> a lab, and they're working to add two more bits. There are >> non-monolithic converters that operate in those ranges as well that >> are commercialized. There may be monolothic converters on the market >> in that range, too... >> >> On Wed, 20 Aug 2003 05:47:57 GMT, ricklyon@REMOVE.onemain.com (Rick >> Lyons) wrote: >> >> > >> >Hi Peter, >> > did you really build a 1 Gsample/sec A/D converter?(!!) >> > >> >I don't even want to *think* about it. >> >I mean, how do you 'breadboard' a circuit that >> >runs at 1 GHz. How do you inject test signals? >> >How do you monitor voltages at different nodes? >> >I checked my Radio Shack catalog and they don't >> >even sell test equipment that operates at 1 GHz. >> > >> >[-Rick-] >> > >> >------------------------------------------- >> >On Mon, 18 Aug 2003 13:32:28 +0200, "John Smith" <piet@bel.com> wrote: >> > >> >>I designed a CIC in VHDL for Altera for our 1 Gs/s ADC. I just parameterised >> >>everything, and used an example from literature to test the design. I am not >> >>an expert in choosing the bit widths. >> >>The comb filters just keeps accumulating samples. The accumulation result >> >>gets bigger and bigger. If you subsample with a factor 16, the accumulation >> >>register should not overflow within that period. I chose a wrong width ones >> >>and did notice wrong results at the output. >> >>regards, >> >>-- >> >>Peter Beukelman >> >>senior ASIC designer >> >>http://www.eonic.com >> >>"Rick Lyons" <ricklyon@REMOVE.onemain.com> wrote in message >> >>news:3f402ef6.115258812@news.west.earthlink.net... >> >>> >> >>> Hi Guys, >> >>> >> >>> I've been trying to learn about those darned cascaded >> >>> integrator-comb (CIC) filters and have reviewed >> >>> Hogenaurer's original paper >> >>> >> >>> Hogenauer, E. "An Economical Class of Digital Filters >> >>> For Decimation and Interpolation," IEEE Trans. Acoust. >> >>> Speech and Signal Proc., Vol. ASSP?29, pp. 155-162, >> >>> April 1981. >> >>> >> >>> and Matt Donadio's CIC write-up (on www.dspguru.com). >> >>> >> >>> But I ran into something concerning CIC interpolators >> >>> that I don't understand and hope you folk might help >> >>> me out. >> >>> >> >>> Hogenauer says (on pp. 160) that there will be bit growth >> >>> (gain) through the interpolator's comb filter(s) >> >>> (differentiators) comprising the initial stage(s) >> >>> of a CIC interpolation filter. He says the bit >> >>> growth will be a factor of 2 >> >>> for each comb filter used in the implementation. >> >>> Because a comb (differentiator) merely outputs >> >>> the difference between successive inputs, I don't see >> >>> how there can be bit growth (gain) through the comb >> >>> stages. >> >>> >> >>> My MATLAB modeling shows no gain (bit growth) in the >> >>> interpolator's comb filters. They have a gain of zero >> >>> at DC. (My modeling agrees with what Ray Andraka has >> >>> stated here, for the gain of a CIC interpolator, >> >>> several times on this newsgroup.) >> >>> >> >>> Anyway, my questions are: is there really bit >> >>> growth (gain) in the initial comb stages of a CIC >> >>> interpolation filter? Am I missing something simple >> >>> here? Do I need to increase the dosage of my medication? >> >>> >> >>> Thanks for any help, >> >>> [-Rick-] >> >>> >> >>> >> >> >> >> >> > >> >> Eric Jacobsen >> Minister of Algorithms, Intel Corp. >> My opinions may not be Intel's opinions. >> http://www.ericjacobsen.org > >-- >--Ray Andraka, P.E. >President, the Andraka Consulting Group, Inc. >401/884-7930 Fax 401/884-7950 >email ray@andraka.com >http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Eric Jacobsen Minister of Algorithms, Intel Corp. My opinions may not be Intel's opinions. http://www.ericjacobsen.org

I didn't do the board design or procurement, so I wasn't privy to the cost of the components. The ADC was an Atmel TS8388. It was a brand new part, we had first been slated to use another ADC and separate mux chip when this was announced. Eric Jacobsen wrote:> Ray, > > Gnarly. Do you recall how expensive that ADC was or how much power > it used? Both parameters are improving quickly these days... > > On Wed, 27 Aug 2003 20:29:37 -0400, Ray Andraka <ray@andraka.com> > wrote: > > >I did an FFT that worked at 960 MHz a year and a half ago in an FPGA. The > >application had an Atmel 1GHz 8 bit ADC coupled to the FPGA, and the FPGA did > >overlapped FFTs on the data in real time. > > > >Eric Jacobsen wrote: > > > >> Rick, > >> > >> Hotrod ADCs with samples rate >=1Gsps are not unusual these days, at > >> least in labs. I know of at least one 4-bit, 1Gsps monolithic ADC in > >> a lab, and they're working to add two more bits. There are > >> non-monolithic converters that operate in those ranges as well that > >> are commercialized. There may be monolothic converters on the market > >> in that range, too... > >> > >> On Wed, 20 Aug 2003 05:47:57 GMT, ricklyon@REMOVE.onemain.com (Rick > >> Lyons) wrote: > >> > >> > > >> >Hi Peter, > >> > did you really build a 1 Gsample/sec A/D converter?(!!) > >> > > >> >I don't even want to *think* about it. > >> >I mean, how do you 'breadboard' a circuit that > >> >runs at 1 GHz. How do you inject test signals? > >> >How do you monitor voltages at different nodes? > >> >I checked my Radio Shack catalog and they don't > >> >even sell test equipment that operates at 1 GHz. > >> > > >> >[-Rick-] > >> > > >> >------------------------------------------- > >> >On Mon, 18 Aug 2003 13:32:28 +0200, "John Smith" <piet@bel.com> wrote: > >> > > >> >>I designed a CIC in VHDL for Altera for our 1 Gs/s ADC. I just parameterised > >> >>everything, and used an example from literature to test the design. I am not > >> >>an expert in choosing the bit widths. > >> >>The comb filters just keeps accumulating samples. The accumulation result > >> >>gets bigger and bigger. If you subsample with a factor 16, the accumulation > >> >>register should not overflow within that period. I chose a wrong width ones > >> >>and did notice wrong results at the output. > >> >>regards, > >> >>-- > >> >>Peter Beukelman > >> >>senior ASIC designer > >> >>http://www.eonic.com > >> >>"Rick Lyons" <ricklyon@REMOVE.onemain.com> wrote in message > >> >>news:3f402ef6.115258812@news.west.earthlink.net... > >> >>> > >> >>> Hi Guys, > >> >>> > >> >>> I've been trying to learn about those darned cascaded > >> >>> integrator-comb (CIC) filters and have reviewed > >> >>> Hogenaurer's original paper > >> >>> > >> >>> Hogenauer, E. "An Economical Class of Digital Filters > >> >>> For Decimation and Interpolation," IEEE Trans. Acoust. > >> >>> Speech and Signal Proc., Vol. ASSP?29, pp. 155-162, > >> >>> April 1981. > >> >>> > >> >>> and Matt Donadio's CIC write-up (on www.dspguru.com). > >> >>> > >> >>> But I ran into something concerning CIC interpolators > >> >>> that I don't understand and hope you folk might help > >> >>> me out. > >> >>> > >> >>> Hogenauer says (on pp. 160) that there will be bit growth > >> >>> (gain) through the interpolator's comb filter(s) > >> >>> (differentiators) comprising the initial stage(s) > >> >>> of a CIC interpolation filter. He says the bit > >> >>> growth will be a factor of 2 > >> >>> for each comb filter used in the implementation. > >> >>> Because a comb (differentiator) merely outputs > >> >>> the difference between successive inputs, I don't see > >> >>> how there can be bit growth (gain) through the comb > >> >>> stages. > >> >>> > >> >>> My MATLAB modeling shows no gain (bit growth) in the > >> >>> interpolator's comb filters. They have a gain of zero > >> >>> at DC. (My modeling agrees with what Ray Andraka has > >> >>> stated here, for the gain of a CIC interpolator, > >> >>> several times on this newsgroup.) > >> >>> > >> >>> Anyway, my questions are: is there really bit > >> >>> growth (gain) in the initial comb stages of a CIC > >> >>> interpolation filter? Am I missing something simple > >> >>> here? Do I need to increase the dosage of my medication? > >> >>> > >> >>> Thanks for any help, > >> >>> [-Rick-] > >> >>> > >> >>> > >> >> > >> >> > >> > > >> > >> Eric Jacobsen > >> Minister of Algorithms, Intel Corp. > >> My opinions may not be Intel's opinions. > >> http://www.ericjacobsen.org > > > >-- > >--Ray Andraka, P.E. > >President, the Andraka Consulting Group, Inc. > >401/884-7930 Fax 401/884-7950 > >email ray@andraka.com > >http://www.andraka.com > > > > "They that give up essential liberty to obtain a little > > temporary safety deserve neither liberty nor safety." > > -Benjamin Franklin, 1759 > > > > > > Eric Jacobsen > Minister of Algorithms, Intel Corp. > My opinions may not be Intel's opinions. > http://www.ericjacobsen.org-- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759