Implementing a Time to Digital Converter in Discrete Time

So I want to use a Time to Digital Converter(TDC) which is used in Time of
Flight Measurements. It normally uses delayed clock samples to achieve a
resolution down to pico second range. I'm not really clear about the
process.
So is it possible to implement a TDC in discrete time domain? I was
thinking of interpolation and low-passing to increase sampling rate.
Simply stated, the problem is this: If an event, (e.g,a leading-edge)
occurs between two leading edges of clock, then is it possible using DSP
techniques to specify the time of the event with a resolution greater than
the clock period?
I've tried to convey the problem but if's still not clear please ask. 
Thank you for your guidance.

	 

_____________________________		
Posted through www.DSPRelated.com

On Sun, 31 Aug 2014 12:17:08 -0500, AWadood7 wrote:

> So I want to use a Time to Digital Converter(TDC) which is used in Time
> of Flight Measurements. It normally uses delayed clock samples to
> achieve a resolution down to pico second range. I'm not really clear
> about the process.
> So is it possible to implement a TDC in discrete time domain? I was
> thinking of interpolation and low-passing to increase sampling rate.
> Simply stated, the problem is this: If an event, (e.g,a leading-edge)
> occurs between two leading edges of clock, then is it possible using DSP
> techniques to specify the time of the event with a resolution greater
> than the clock period?
> I've tried to convey the problem but if's still not clear please ask.
> Thank you for your guidance.

Some sort of analog whiz-bang has to be there.  It may be as simple as the 
lowpass filter that you alluded to, so that the "leading edge" is spread 
over several samples.  It could be as complicated as an integrator that 
starts charging on the leading edge of the event, and is sampled by and 
ADC at a clock tick, and then stops.

You can't just feed a square wave into a comparator, sample the comparator 
output, and get an answer to higher resolution than your sampling rate.

You would probably need to take your event, clean it up to some well-
defined amplitude with a really fast comparator, then low-pass the thing 
(a 1st-order lowpass should work as long as your repetition rate isn't too 
high, although it may not be best).  Finally, take some samples with a 
nice stable high-precision ADC, and do some math to back out a time-of-
arrival.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

On 8/31/2014 2:33 PM, Tim Wescott wrote:
> On Sun, 31 Aug 2014 12:17:08 -0500, AWadood7 wrote:
>
>> So I want to use a Time to Digital Converter(TDC) which is used in Time
>> of Flight Measurements. It normally uses delayed clock samples to
>> achieve a resolution down to pico second range. I'm not really clear
>> about the process.
>> So is it possible to implement a TDC in discrete time domain? I was
>> thinking of interpolation and low-passing to increase sampling rate.
>> Simply stated, the problem is this: If an event, (e.g,a leading-edge)
>> occurs between two leading edges of clock, then is it possible using DSP
>> techniques to specify the time of the event with a resolution greater
>> than the clock period?
>> I've tried to convey the problem but if's still not clear please ask.
>> Thank you for your guidance.
>
> Some sort of analog whiz-bang has to be there.  It may be as simple as the
> lowpass filter that you alluded to, so that the "leading edge" is spread
> over several samples.  It could be as complicated as an integrator that
> starts charging on the leading edge of the event, and is sampled by and
> ADC at a clock tick, and then stops.
>
> You can't just feed a square wave into a comparator, sample the comparator
> output, and get an answer to higher resolution than your sampling rate.
>
> You would probably need to take your event, clean it up to some well-
> defined amplitude with a really fast comparator, then low-pass the thing
> (a 1st-order lowpass should work as long as your repetition rate isn't too
> high, although it may not be best).  Finally, take some samples with a
> nice stable high-precision ADC, and do some math to back out a time-of-
> arrival.

The OP has an idea of how to do this.  He talks about delayed clock 
samples.  This is possible in an FPGA using a DLL.  I don't recall the 
details of how this works, but I know you can specify the delay down to 
some smallish number of picoseconds(50 ps maybe?).  For a repetitive 
event this is duck soup.  For a one shot event I'm not sure.  I don't 
think you can generate more than one delay at a time.

Another way is to step up your clock rate using the DLL.  The leading 
edge can be clocked into a SERDES at some 16x the input clock rate (or 
more) and the word read out giving the location of the leading edge.

Even so this will only give you resolution to 100 ps ballpark I expect. 
  I don't know the exact upper limit of the typical SERDES in FPGAs.  I 
do know they are in the GHz range and vary.

If you can apply brute force like they do in flash converters, you can 
create a large number of delay lines and use one input per delay line. 
Then your precision is only limited by the consistency of the delay from 
the clock pin to the input FFs.  I expect you can get down to the 10 ps 
ballpark without too much trouble, but don't really know.

-- 

Rick

>Some sort of analog whiz-bang has to be there.  It may be as simple as the

>lowpass filter that you alluded to, so that the "leading edge" is spread 
>over several samples.  It could be as complicated as an integrator that 
>starts charging on the leading edge of the event, and is sampled by and 
>ADC at a clock tick, and then stops.
>
>You can't just feed a square wave into a comparator, sample the comparator

>output, and get an answer to higher resolution than your sampling rate.
>
>You would probably need to take your event, clean it up to some well-
>defined amplitude with a really fast comparator, then low-pass the thing 
>(a 1st-order lowpass should work as long as your repetition rate isn't too

>high, although it may not be best).  Finally, take some samples with a 
>nice stable high-precision ADC, and do some math to back out a time-of-
>arrival.
>
>-- 
>
>Tim Wescott
>Wescott Design Services
>http://www.wescottdesign.com

In the first para:
1)The leading edge itself is 2ns wide. How can I recover that with a
low-pass filter?
I don't understand the process in the last paragraph. Please elaborate.	 

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Posted through www.DSPRelated.com

>The OP has an idea of how to do this.  He talks about delayed clock 
>samples.  This is possible in an FPGA using a DLL.  I don't recall the 
>details of how this works, but I know you can specify the delay down to 
>some smallish number of picoseconds(50 ps maybe?).  For a repetitive 
>event this is duck soup.  For a one shot event I'm not sure.  I don't 
>think you can generate more than one delay at a time.
>
>Another way is to step up your clock rate using the DLL.  The leading 
>edge can be clocked into a SERDES at some 16x the input clock rate (or 
>more) and the word read out giving the location of the leading edge.
>
>Even so this will only give you resolution to 100 ps ballpark I expect. 
>  I don't know the exact upper limit of the typical SERDES in FPGAs.  I 
>do know they are in the GHz range and vary.
>
>If you can apply brute force like they do in flash converters, you can 
>create a large number of delay lines and use one input per delay line. 
>Then your precision is only limited by the consistency of the delay from 
>the clock pin to the input FFs.  I expect you can get down to the 10 ps 
>ballpark without too much trouble, but don't really know.
>
>-- 
>
>Rick
>
I know this could be implemented in FPGAs to 100ps(500ps would work fine
for me.) I was asking about discrete-time domain, like a method involving
offline processing of samles and then using math to increase the
resolution.	 

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On 8/31/2014 3:57 PM, AWadood7 wrote:
>>
> I know this could be implemented in FPGAs to 100ps(500ps would work fine
> for me.) I was asking about discrete-time domain, like a method involving
> offline processing of samles and then using math to increase the
> resolution.	

I'm not clear on what you are thinking.  What sort of "samples" could 
you process "offline"?  If it is digital you need to have something to 
process.  I think that is where the analog ideas come in.

-- 

Rick

On 8/31/2014 3:47 PM, AWadood7 wrote:
>> Some sort of analog whiz-bang has to be there.  It may be as simple as the
>
>> lowpass filter that you alluded to, so that the "leading edge" is spread
>> over several samples.  It could be as complicated as an integrator that
>> starts charging on the leading edge of the event, and is sampled by and
>> ADC at a clock tick, and then stops.
>>
>> You can't just feed a square wave into a comparator, sample the comparator
>
>> output, and get an answer to higher resolution than your sampling rate.
>>
>> You would probably need to take your event, clean it up to some well-
>> defined amplitude with a really fast comparator, then low-pass the thing
>> (a 1st-order lowpass should work as long as your repetition rate isn't too
>
>> high, although it may not be best).  Finally, take some samples with a
>> nice stable high-precision ADC, and do some math to back out a time-of-
>> arrival.
>>
>> --
>>
>> Tim Wescott
>> Wescott Design Services
>> http://www.wescottdesign.com
>
> In the first para:
> 1)The leading edge itself is 2ns wide. How can I recover that with a
> low-pass filter?
> I don't understand the process in the last paragraph. Please elaborate.	

I think he is saying to use a comparator to set a consistent trigger 
point and to give the waveform a sharp edge.  Then use a filter to give 
it a well defined slope.  Sample with an ADC and you get a measurement 
of the timing of the edge by measuring the voltage on that slope.

Maybe you can do this with the existing pulse shape if it is consistent 
in shape and amplitude.  2 ns would be a reasonable rise time if you 
have a clock rate above 500 MHz.

It won't take too much processing to get a time from the ADC output. 
You may want to correct for the exact shape of the pulse edge with a 
non-linear equation.

-- 

Rick

On Sun, 31 Aug 2014 14:47:18 -0500, AWadood7 wrote:

>>Some sort of analog whiz-bang has to be there.  It may be as simple as
>>the
> 
>>lowpass filter that you alluded to, so that the "leading edge" is spread
>>over several samples.  It could be as complicated as an integrator that
>>starts charging on the leading edge of the event, and is sampled by and
>>ADC at a clock tick, and then stops.
>>
>>You can't just feed a square wave into a comparator, sample the
>>comparator
> 
>>output, and get an answer to higher resolution than your sampling rate.
>>
>>You would probably need to take your event, clean it up to some well-
>>defined amplitude with a really fast comparator, then low-pass the thing
>>(a 1st-order lowpass should work as long as your repetition rate isn't
>>too
> 
>>high, although it may not be best).  Finally, take some samples with a
>>nice stable high-precision ADC, and do some math to back out a time-of-
>>arrival.
>>
>>--
>>
>>Tim Wescott Wescott Design Services http://www.wescottdesign.com
> 
> In the first para:
> 1)The leading edge itself is 2ns wide. How can I recover that with a
> low-pass filter?

You don't recover the leading edge -- you purposely smear it out.

> I don't understand the process in the last paragraph. Please elaborate.

If you just sample a square edge you get a square edge, and you don't know 
when it happened.

If you sample a square edge that's been low-pass filtered, then you get at 
least one -- possibly more -- samples between low and high.  The 
amplitudes of these samples will vary with the arrival time of the edge in 
a known way.  You measure the voltage of the samples, then use the known 
relationship between time and voltage to calculate time from voltage.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

AWadood7 <101492@dsprelated> wrote:

> So I want to use a Time to Digital Converter(TDC) which is used in 
> Time of Flight Measurements. It normally uses delayed clock 
> samples to achieve a resolution down to pico second range. 
> I'm not really clear about the process.

The ones I know charge a capacitor at constant current, then
measure the voltage at the appropriate time using and ADC.

I am not sure how they are calibrated. I could imagine a PLL
system that keeps the charging current just right, but it might
be that you just adjust the current as appropriate. 

> So is it possible to implement a TDC in discrete time domain? 
> I was thinking of interpolation and low-passing to increase 
> sampling rate.

Not that I can think of, but maybe others can. You mean a digital
low-pass filter, not an analog one?

> Simply stated, the problem is this: If an event, (e.g,a leading-edge)
> occurs between two leading edges of clock, then is it possible using DSP
> techniques to specify the time of the event with a resolution greater than
> the clock period?

> I've tried to convey the problem but if's still not clear please ask. 

Some years ago, I was working on PET scanner design, which use TDCs
to determine the time difference between the signal reaching two
detectors to high resolution, though maybe not high accuracy.

-- glen

On 31/08/14 18:17, AWadood7 wrote:
> So I want to use a Time to Digital Converter(TDC) which is used in Time of
> Flight Measurements. It normally uses delayed clock samples to achieve a
> resolution down to pico second range. I'm not really clear about the
> process.
> So is it possible to implement a TDC in discrete time domain? I was
> thinking of interpolation and low-passing to increase sampling rate.
> Simply stated, the problem is this: If an event, (e.g,a leading-edge)
> occurs between two leading edges of clock, then is it possible using DSP
> techniques to specify the time of the event with a resolution greater than
> the clock period?
> I've tried to convey the problem but if's still not clear please ask.
> Thank you for your guidance.

http://www.ko4bb.com/~bruce/TDC.html