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ADSP-2116x PC register format

Started by marc-f June 29, 2003
Hello,

I'm working on the ADSP-21160, and I wanted to know what is the format
of the PC register. In the Hardware Reference (2nd ed), page A-36, it is
written that DM/PM addresses buses have the following format :

|31     23|22     20|19     17|16                                0|
| E Field | M field | S field |               address             |

But the sequencer uses 24 bit addresses (especially for PC register, or
field in LADDR). What is the format? Which memory spaces is addressed
(internal memory? internal memory of other dsp ? extern memory included
?). I didn't find anything in the doc (neither HR, nor Instruction Set
Reference).

And about the I register (or direct data32 address), do we have to take
care about this format ? And what happend if the instruction tell it's 
a LW transfer (with a Normal-word address for the I register/data32).


Thanks for any help provided.



Marc Finet


PS: sorry, if the message is posted twice (i wanna remove one), but my
old post-server seems strange.
The Sun, 29 Jun 2003 16:01:48 +0200 marc-f <mAaNrTcIfSiPnAeMt@free.fr>
wrote

> > Hello, > > I'm working on the ADSP-21160, and I wanted to know what is the format > of the PC register. In the Hardware Reference (2nd ed), page A-36, it > is written that DM/PM addresses buses have the following format : > > |31 23|22 20|19 17|16 0| > | E Field | M field | S field | address | > > But the sequencer uses 24 bit addresses (especially for PC register, > or field in LADDR). What is the format?
It seems that it's only a 24 bit address for 48 bits acces.
> And about the I register (or direct data32 address), do we have to > take care about this format ?
Yes. But i have new questions (and I didn't receive the VisualDSP trial version to run tests): 1. What happend for short-word address transfer like below: for example : MODE1 = DM(0x0008000) According to the E/S/M decomposition, the 0x008000 is a shord-word transfer (S=100). In the examples on doc, only short-word transfor for/form Data Register (R/S) are given. Is there a 16 bit transfer ? With sign extension (depending on SSE bit). 2. About the interuptions (with NESTM), what does the IMASKP register reflects? Interuptions that have been interupted by higest priority ones, and the interuption which is currently serviced ? At the return of interuption (RTI), what the sequencer does ? It's said in the doc, that the top of PC stack is poped and the PC is set by it's value. But, if there was an interuption that have been interupted (due to priority), the PC stack must not change ! Could someone correct the following schedule ? (Assuming, all interupt are enabled). I use numbers for interupts(0:highest priority, 31:lowest). Cycle|Int. |Interupt|Interupt waiting| Interupt |occur|serviced| (in IRPTL) |Interupted -----+-----+--------+----------------+----------- 00 | | | | 01 |16,15| | | 02 | | | | 03 | 20 | 16 | 15 | 04 | | 15 | 16 | 16 05 | 10 | 15 | 20,16 | 16 06 | | 15 | 20,16 | 16 07 | | 10 | 20,16,15 | 16,15 08 | 12 | 10 | 20,16,15 | 16,15 09 | | 10 | 20,16,15 | 16,15 10 | | 10(RTI)| 20,16,15,12 | 16,15 11 | 13 | 12 | 20,16,15 | 16,15 12 | | 12(RTI)| 20,16,15 | 16,15 13 | | 13(RTI)| 20,16,15 | 16,15 14 | | 15 | 20,16 | 16 15 | | 15(RTI)| 20,16 | 16 16 | | 16(RTI)| 20 | 17 | | 20(RTI)| | Regards, Marc.