Hi all ,
I am new to the concept of McBSP. Can any body give the
programming guide lines of configuring the McBSP ( SPI) of TMS320C55x or
TMS320C54x
Thank u in advance,
Sai Kumar
How Can i Initialise McBSP of TMS320C55X
Started by ●September 3, 2004
Reply by ●September 3, 20042004-09-03
"Sai Kumar" <saikumar.s@in.bosch.com> wrote in message news:ch8trk$civ$1@ns1.fe.internet.bosch.com...> Hi all , > I am new to the concept of McBSP. Can any body give the > programming guide lines of configuring the McBSP ( SPI) of TMS320C55x or > TMS320C54x > > Thank u in advance, > > Sai Kumar >The McBSP Reference Guide is a good place to start: http://focus.ti.com/lit/ug/spru592d/spru592d.pdf Chapter 6 covers SPI mode. Brad
Reply by ●September 3, 20042004-09-03
"Sai Kumar" <saikumar.s@in.bosch.com> wrote in message news:<ch8trk$civ$1@ns1.fe.internet.bosch.com>...> Hi all , > I am new to the concept of McBSP. Can any body give the > programming guide lines of configuring the McBSP ( SPI) of TMS320C55x or > TMS320C54x > > Thank u in advance, > > Sai Kumar/////////////////////////////////////////////////////////////// Sai, Here are some snips of a c and h file to set mcbsp2 as a SPI port Hope it gets you started Phil / peejayblack /////////////////////////////////////////////////////////////// //// >>>> h file #define C55XX_MCBSP0_ADDR 0x2800 #define C55XX_MCBSP1_ADDR 0x2C00 #define C55XX_MCBSP2_ADDR 0x3000 /*============================================*/ /*===========================================*/ //==== Multi-channel serial port typedef struct c55xx_mcsp { unsigned short ddr2; /*00 */ unsigned short ddr1; /*01 */ unsigned short dxr2; /*02 */ unsigned short dxr1; /*03 */ unsigned short spcr2; /*04 */ unsigned short spcr1; /*05 */ unsigned short rcr2; /*06 */ unsigned short rcr1; /*07 */ unsigned short xcr2; /*08 */ unsigned short xcr1; /*09 */ unsigned short srgr2; /*0A */ unsigned short srgr1; /*0B */ unsigned short mcr2; /*0C */ unsigned short mcr1; /*0D */ unsigned short rcera; /*0E */ unsigned short rcerb; /*0F */ unsigned short xcera; /*10 */ unsigned short xcerb; /*11 */ unsigned short pcr; /*12 */ unsigned short pcerc; /*13 */ unsigned short pcerd; /*14 */ unsigned short xcerc; /*15 */ unsigned short xcerd; /*16 */ unsigned short rcere; /*17 */ unsigned short rcerf; /*18 */ unsigned short xcere; /*19 */ unsigned short xcerf; /*1A */ unsigned short rcerg; /*1B */ unsigned short rcerh; /*1C */ unsigned short xcerg; /*1D */ unsigned short xcerh; /*1E */ }C55XX_MCBSP; typedef ioport volatile C55XX_MCBSP *PC55XX_MCBSP; /*====================================================== */ #define McBSP_DRR2_3 0x3000 #define McBSP_DRR1_3 0x3001 #define McBSP_DXR2_3 0x3002 #define McBSP_DXR1_3 0x3003 #define McBSP_SPCR1_3 0x3005 #define McBSP_SPCR2_3 0x3004 #define McBSP_RCR2_3 0x3006 #define McBSP_RCR1_3 0x3007 #define McBSP_XCR2_3 0x3008 #define McBSP_XCR1_3 0x3009 #define McBSP_SRGR2_3 0x300A #define McBSP_SRGR1_3 0x300B #define McBSP_PCR_3 0x3012 //#define IER0 0x0000 /* Interrupt enable register 0 */ /* Configure the McBSP receiver for SPI Master mode */ //=========================================================================== //= SOP initialization constants for mcbsp //=========================================================================== SPCR1 //- | MSB | | | LSB | MSB LSB //- --------------------------------------------------- //- +---- 1 DLB -- RJUST -- CLKSTP1 | 0 0 0 1 //- |+--- 8 CLKSTP0 xx xx xx | 1 0 0 0 //- ||+-- 0 DXENA ABIS -- RINTM -- | 0 0 0 0 //- |||+- 0 RSYNCERR RFULL RRDY ~RRST | 0 0 0 0 //- |||| #define SPI_SPCR1 0x1800 // same as above w enable recv #define SPI_RCV_RESET (SPI_SPCR1 | 0x0000) #define SPI_RCV_ENAB (SPI_SPCR1 | 0x0001) //=========================================================================== SPCR2 //- | MSB | | | LSB | MSB LSB //- --------------------------------------------------- //- +---- 0 xx xx xx xx | 0 0 0 0 //- |+--- 2 xx xx FREE SOFT | 0 0 1 0 //- ||+-- 0 ~FRST ~GRST -- XINTM -- | 0 0 0 0 //- |||+- 0 XSYNCERR ~XEMPTY XRDY ~XRST | 0 0 0 0 //- |||| #define SPI_SPCR2 0x0200 #define XRST_ENAB 0x0001 #define GRST_ENAB 0x0040 //=========================================================================== RCR1 SPI 16 //- | MSB | | | LSB | MSB LSB //- --------------------------------------------------- //- +---- 0 xx RFRLEN1-6 ------ RFRLEN1-4 | 0 0 0 0 //- |+--- 0 RFRLEN1-3 --------------- RFRLEN1-0 | 0 0 0 0 //- ||+-- 4 RWDLEN1-2 ----- RWDLEN1-0 xx | 0 1 0 0 //- |||+- 0 xx xx xx xx | 0 0 0 0 //- |||| #define SPI_RCR1_16 0x0040 //=========================================================================== RCR1 SPI 12 //- | MSB | | | LSB | MSB LSB //- --------------------------------------------------- //- +---- 0 xx RFRLEN1-6 ------ RFRLEN1-4 | 0 0 0 0 //- |+--- 0 RFRLEN1-3 --------------- RFRLEN1-0 | 0 0 0 0 //- ||+-- 2 RWDLEN1-2 ----- RWDLEN1-0 xx | 0 0 1 0 //- |||+- 0 xx xx xx xx | 0 0 0 0 //- |||| #define SPI_RCR1_12 0x0020 //=========================================================================== RCR1 SPI 8 //- | MSB | | | LSB | MSB LSB //- --------------------------------------------------- //- +---- 0 xx RFRLEN1-6 ------ RFRLEN1-4 | 0 0 0 0 //- |+--- 0 RFRLEN1-3 --------------- RFRLEN1-0 | 0 0 0 0 //- ||+-- 0 RWDLEN1-2 ----- RWDLEN1-0 xx | 0 0 0 0 //- |||+- 0 xx xx xx xx | 0 0 0 0 //- |||| #define SPI_RCR1_8 0x0000 //=========================================================================== RCR2 //- | MSB | | | LSB | MSB LSB //- --------------------------------------------------- //- +---- 0 RPHASE RFRLEN2-6 ------- RFRLEN2-4 | 0 0 0 0 //- |+--- 0 RFRLEN2-3 --------------- RFRLEN2-0 | 0 0 0 0 //- ||+-- 0 RWDLEN2 -------- RWDLEN2 RCOMPAND | 0 0 0 0 //- |||+- 1 RCOMPAND RFIG -- RDATDLY -- | 0 0 0 1 //- |||| #define SPI_RCR2 0x0001 //=========================================================================== XCR1 SPI 16 BITS //- | MSB | | | LSB | MSB LSB //- --------------------------------------------------- //- +---- 0 xx XFRLEN1-6 ------ XFRLEN1-4 | 0 0 0 0 //- |+--- 0 XFRLEN1-3 --------------- XFRLEN1-0 | 0 0 0 0 //- ||+-- 4 XWDLEN1-2 ----- XWDLEN1-0 xx | 0 1 0 0 //- |||+- 0 xx xx xx xx | 0 0 0 0 //- |||| #define SPI_XCR1_16 0x0040 //=========================================================================== XCR1 SPI 12 BITS //- | MSB | | | LSB | MSB LSB //- --------------------------------------------------- //- +---- 0 xx XFRLEN1-6 ------ XFRLEN1-4 | 0 0 0 0 //- |+--- 0 XFRLEN1-3 --------------- XFRLEN1-0 | 0 0 0 0 //- ||+-- 2 XWDLEN1-2 ----- XWDLEN1-0 xx | 0 0 1 0 //- |||+- 0 xx xx xx xx | 0 0 0 0 //- |||| #define SPI_XCR1_12 0x0020 //=========================================================================== XCR1 SPI 8 BITS //- | MSB | | | LSB | MSB LSB //- --------------------------------------------------- //- +---- 0 xx XFRLEN1-6 ------ XFRLEN1-4 | 0 0 0 0 //- |+--- 0 XFRLEN1-3 --------------- XFRLEN1-0 | 0 0 0 0 //- ||+-- 0 XWDLEN1-2 ----- XWDLEN1-0 xx | 0 0 0 0 //- |||+- 0 xx xx xx xx | 0 0 0 0 //- |||| #define SPI_XCR1_8 0x0000 //=========================================================================== XCR2 //- | MSB | | | LSB | MSB LSB //- --------------------------------------------------- //- +---- 0 XPHASE XFRLEN2-6 ------- XFRLEN2-4 | 0 0 0 0 //- |+--- 0 XFRLEN2-3 --------------- XFRLEN2-0 | 0 0 0 0 //- ||+-- 0 XWDLEN2 -------- XWDLEN2 XCOMPAND | 0 0 0 0 //- |||+- 1 XCOMPAND XFIG -- XDATDLY -- | 0 0 0 1 //- |||| #define SPI_XCR2 0x0001 //=========================================================================== SRGR1 //- | MSB | | | LSB | MSB LSB //- --------------------------------------------------- //- +---- 0 FWID-15 -------------------------- | 0 0 0 0 //- |+--- 0 ------------------------ FWID-0 | 0 0 0 0 //- ||+-- 0 CLKGDV-7 ------------------------- | 0 0 0 0 //- |||+- 0 --------------------- CLKDV-0 | 0 0 0 1 //- |||| #define SPI_SRGR1 0x0020 //=========================================================================== SRGR2 //- | MSB | | | LSB | MSB LSB //- --------------------------------------------------- //- +---- 2 GSYNC CLKSP CLKSM FSGM | 0 0 1 0 //- |+--- 0 FPER-11 ------------------------- | 0 0 0 0 //- ||+-- 0 ----------------------------- | 0 0 0 0 //- |||+- 0 ----------------------- FPER-0 | 0 0 0 0 //- |||| #define SPI_SRGR2 0x2000 //=========================================================================== PCR //- | MSB | | | LSB | MSB LSB //- --------------------------------------------------- //- +---- 0 xx IDLEEN XIOEN RIOEN | 0 0 0 0 //- |+--- a FSXM FSRM CLKXM CLKRM | 1 0 1 0 //- ||+-- 0 xx CLKS_STAT DX_STAT DR_STAT | 0 0 0 0 //- |||+- 8 FSXP FSRP CLKXP CLKRP | 1 0 0 0 //- |||| //#define SPI_PCR 0x0a08 #define SPI_PCR 0x0f0d //================================================ //- force defaults #define SPI_MCRx 0x0000 //- Multichannel reg #define SPI_RCERx 0x0000 //- Receive chan enab reg #define SPI_XCERx 0x0000 //- Transmit chan enab reg //======================================== // >>>>> c file //==================================== void mcbsp2_ini(void) { u16 temp; PC55XX_MCBSP pMcBSP = (PC55XX_MCBSP)C55XX_MCBSP2_ADDR ; pMcBSP -> spcr1 = SPI_SPCR1; // 05 ini and reset receiver pMcBSP -> spcr2 = SPI_SPCR2; // 04 ini and reset transmitter pMcBSP -> rcr1 = SPI_RCR1_8; // 07 pMcBSP -> rcr2 = SPI_RCR2; // 06 pMcBSP -> xcr1 = SPI_XCR1_8; // 09 pMcBSP -> xcr2 = SPI_XCR2; // 08 pMcBSP -> srgr1 = SPI_SRGR1; // 0B pMcBSP -> srgr2 = SPI_SRGR2; // 0A //- force defaults pMcBSP -> mcr1 = SPI_MCRx; // 0D pMcBSP -> mcr2 = SPI_MCRx; // 0C pMcBSP -> rcera = SPI_RCERx; // 0E pMcBSP -> rcerb = SPI_RCERx; // 0F pMcBSP -> xcera = SPI_XCERx; // 10 pMcBSP -> xcerb = SPI_XCERx; // 11 temp = pMcBSP -> spcr2; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; pMcBSP -> spcr2 = (temp | GRST_ENAB); /*04 */ for ( temp =0; temp<10000; temp++ ) { NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; } NOP; temp = pMcBSP -> spcr2; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; pMcBSP -> spcr2 = (temp | GRST_ENAB | XRST_ENAB); /*04 */ NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; pMcBSP -> pcr = SPI_PCR; /*12 */ }
Reply by ●September 6, 20042004-09-06
Hi Philblack and Brad Cain,
Thank you very much for your support. I am really happy.
Regards,
Sai Kumar
"Brad Griffis" <bradgriffis@hotmail.com> wrote in message
news:SKZZc.7262$ZC7.3629@newssvr19.news.prodigy.com...
> "Sai Kumar" <saikumar.s@in.bosch.com> wrote in message
> news:ch8trk$civ$1@ns1.fe.internet.bosch.com...
> > Hi all ,
> > I am new to the concept of McBSP. Can any body give the
> > programming guide lines of configuring the McBSP ( SPI) of TMS320C55x or
> > TMS320C54x
> >
> > Thank u in advance,
> >
> > Sai Kumar
> >
>
> The McBSP Reference Guide is a good place to start:
>
> http://focus.ti.com/lit/ug/spru592d/spru592d.pdf
>
> Chapter 6 covers SPI mode.
>
> Brad
>
>
