C6713 and SDRAM

Hi,

Recently I have a DSP project in which TMS6713BPYP is used. I have
problem to interface the C6713 to the 16 bit SDRAM HY57V16160E. The CCS
always prompt a message soemthing like "Please verify target memory and
memory map". I am quite sure that it is not software problem as the
program can be loaded to the DSK6713.

Could anyone check for me whether the following connections correct?
Thank you very much for any hints.

HY57V16160E-------------C6713
------------------------------------
CLK---------------------ECLKOUT
LDQM--------------------\BE0
UDQM--------------------\BE1
\WE---------------------\SDWE
\CAS--------------------\SDCAS
\RAS--------------------\SDRAS
\CS---------------------\CE0
DQ0-15------------------ED0-15
A0-11------------------EA2-13
VDD---------------------3.3V
VDDQ--------------------3.3V
VSS---------------------GND
VSSQ--------------------GND

In comp.dsp,
eeh <eehobbyist@yahoo.com.hk> wrote:
>Hi,
>
>Could anyone check for me whether the following connections correct?
>Thank you very much for any hints.
>
>HY57V16160E-------------C6713
>------------------------------------
>CLK---------------------ECLKOUT
>LDQM--------------------\BE0
>UDQM--------------------\BE1
>\WE---------------------\SDWE
>\CAS--------------------\SDCAS
>\RAS--------------------\SDRAS
>\CS---------------------\CE0
>DQ0-15------------------ED0-15
>A0-11------------------EA2-13
>VDD---------------------3.3V
>VDDQ--------------------3.3V
>VSS---------------------GND
>VSSQ--------------------GND
>
[Could not find the HY57V16160E datasheet so took a quick look at the
HY57V161610E datasheet and may therefore be talking bullocks. :-)]

Where did you connect the HY57V16160E CKE to? Are there no BA lines on the
SDRAM chip? I don't know the C6713, but in a current design whe use a arm
chip that has a special output for SDA10 and you have to use that instead
of the normal A12. Re-check the SDRAM interface in the C6713 datasheet.

The rest looks OK at first glance.

-- 
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

Behind every great man, there is a woman -- urging him on.
		-- Harry Mudd, "I, Mudd", stardate 4513.3

Sorry, the SDRAM should be HY57V161610E.

In comp.dsp,
eeh <eehobbyist@yahoo.com.hk> wrote:
>Sorry, the SDRAM should be HY57V161610E.
>
Hey, that's the datasheet I looked at. :-)
So what about CKE?

-- 
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

As you grow older, you will still do foolish things, but you will do them
with much more enthusiasm.
		-- The Cowboy

Sorry, CKE is high.

Hi,

Your wiring diagram looks fine to me.

A Simple thing to do as a sanity check would be to open a memory window
in CCS on the chip select you are using, and try to edit the window.

For example, change one of the addresses to 0x12345678.

Then REFRESH the window (perhaps a few times).  If the value doesn't
'stick' or if you can see other addresses change (highlighted in RED)
then you probably have a hardware problem or an initialization problem,
and the error is because CCS isn't verifying that the download was
ok.

Then I would recommend checking some additional items:

  o EMIF clock pin.  This is the most critical trace for functionality, so
     hopefully it is short and doesn't have signal integrity problems.
     If it does, try adding a series terminator near the DSP.

  o boot mode pins.  see http://focus.ti.com/lit/ds/symlink/tms320c6713.pdf
     on pages 33-35. It would be a good idea to go through these as
     some of the pins discussed affect the EMIF or the endian of the device.

  o DEVCFG register - On page 36, the EKSRC bit affects the selection
     of EMIF clock.  So if this is not set correctly, the clock to SDRAM may
     be at a different frequency then you would think.

  o The EMIF control registers.  I am not sure how these are configured on
     the DSK.  It could be done with code from flash or a GEL file.

     But with your own board, you would need to program the correct
     SDRAM geometry and refresh before you can correctly write to the SDRAM.

    There is some good information in this document.
         http://focus.ti.com/lit/an/spra433d/spra433d.pdf

     The above covers different DSPs but for 6713 you can look at the 6211
     discussion because except for boot up differences and the EKSRC option,
     the EMIFs are the same.

o  If nothing else above helped  I would check for
    assembly problems (loose or shorted pins).

 Just some ideas.  Good luck with your project.

-Anthony




"eeh" <eehobbyist@yahoo.com.hk> wrote in message
news:1116858405.683516.115790@g14g2000cwa.googlegroups.com...
> Hi,
>
> Recently I have a DSP project in which TMS6713BPYP is used. I have
> problem to interface the C6713 to the 16 bit SDRAM HY57V16160E. The CCS
> always prompt a message soemthing like "Please verify target memory and
> memory map". I am quite sure that it is not software problem as the
> program can be loaded to the DSK6713.
>
> Could anyone check for me whether the following connections correct?
> Thank you very much for any hints.
>
> HY57V16160E-------------C6713
> ------------------------------------
> CLK---------------------ECLKOUT
> LDQM--------------------\BE0
> UDQM--------------------\BE1
> \WE---------------------\SDWE
> \CAS--------------------\SDCAS
> \RAS--------------------\SDRAS
> \CS---------------------\CE0
> DQ0-15------------------ED0-15
> A0-11------------------EA2-13
> VDD---------------------3.3V
> VDDQ--------------------3.3V
> VSS---------------------GND
> VSSQ--------------------GND
>

Thanks!

I also think the circuit is right and I estimate the settings in the
GEL file is incorrect. I find there are 3 SDRAM registers which needs
to be set. They are:

EMIF_SDRAMCTL
EMIF_SDRAMTIM
EMIF_SDRAMEXT

I have set them to

EMIF_SDRAMCTL=0x07117000
EMIF_SDRAMTIM=0x005dc5dc
EMIF_SDRAMEXT=0x000dfdff

Are they right?

Moreover, how to set DEVCFG register in GEL?